NAND04GW3C2N1E データシートの表示（PDF） - STMicroelectronics

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NAND04GW3C2N1E

4Gbit, 2112 Byte Page, 3V, Multi-level NAND Flash Memory

STMicroelectronics 

6 Device operations

NAND04GA3C2A, NAND04GW3C2A

Table 9. Status Register Bits

Bit

Name

Logic Level

Definition

SR7

SR6(1)

Write Protection

Program/ Erase/ Read

Controller

Cache Ready/Busy

'1'

Not Protected

'0'

Protected

'1'

P/E/R C inactive, device ready

'0'

P/E/R C active, device busy

'1'

Cache Register ready (Cache Read only)

'0'

Cache Register busy (Cache Read only)

SR5

SR4, SR3,

SR2, SR1

SR0(1)

Program/ Erase/ Read

Controller(2)

Reserved

Generic Error

'1'

'0'

Don’t Care

‘1’

‘0’

P/E/R C inactive

P/E/R C active

Error – operation failed

No Error – operation successful

1. The SR6 bit and SR0 bit have a different meaning during Cache Read operations.

2. Only valid for Cache Read operations, for other operations it is same as SR6.

6.11

Read Electronic Signature

The device contains a Manufacturer Code and Device Code. To read these codes three steps

are required:

1. One Bus Write cycle to issue the Read Electronic Signature command (90h)

2. One Bus Write cycle to input the address (00h)

3. Four Bus Read Cycles to sequentially output the data (as shown in Table 10: Electronic

Signature).

Table 10. Electronic Signature

Byte/Word 1

Part Number

Manufacturer

Code

NAND04GA3C2A

20h

NAND04GW3C2A

20h

Byte/Word 2

Device code

DCh

DCh

Byte 3

(see Table 11)

84h

84h

Byte 4

(see Table 12)

25h

26/51

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