AU80610006237AASLBX9 データシートの表示（PDF） - Intel
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AU80610006237AASLBX9 Datasheet PDF : 88 Pages
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Signal Description
Table 2-4. System Memory Interface
Signal Name
Description
DDR_A_DM_[7:0]
DDR_A_DQS_[7:0]
DDR_A_DQS#_[7:0]
DDR_A_ODT_[3:0]
Data Mask: These signals are used to mask
individual bytes of data in the case of a partial
write, and to interrupt burst writes.
When activated during writes, the
corresponding data groups in the SDRAM are
masked. There is one DDR_A_DM_[7:0] for
every data byte lane.
Data Strobes: DDR_A_DQS_[7:0] and its
complement signal group make up a
differential strobe pair. The data is captured at
the crossing point of DDR_A_DQS_[7:0] and
its DDR_A_DQS#_[7:0] during read and write
transactions.
Data Strobe Complements: These are the
complementary strobe signals.
On-Die-Termination: Active Termination
Control
Direction Type
O
SSTL-1.8
I/O
SSTL-1.8
I/O
SSTL-1.8
O
SSTL-1.8
Table 2-5. Memory Reference and Compensation
Signal
Name
DDR_RPD
DDR_RPU
DDR_VREF
Description
System Memory RCOMP signal.
System Memory RCOMP signal.
SDRAM Reference Voltage
2.3
Reset and Miscellaneous Signals
Direction Type
I/O
Analog
I/O
Analog
I
Analog
Table 2-6. Reset and Miscellaneous Signals (Sheet 1 of 2)
Signal Name
Description
Direction Type
RSTIN#
PWROK
Reset In: When asserted, this signal will
asynchronously reset the CPU logic. The signal is
connected to the PLTRST# output of the south
bridge.
This input should have a Schmitt trigger to avoid
spurious resets.
This signal is required to be 3.3-V tolerant.
I
HVCMOS
Power OK: When asserted, PWROK is an
I
HVCMOS
indication to the processor that core power has
been stable.
This input should have a Schmitt trigger to avoid
spurious resets. This signal is required to be 3.3-
V tolerant.
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Datasheet
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