ADUM1400(2004) データシートの表示（PDF） - Analog Devices
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ADUM1400 Datasheet PDF : 24 Pages
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ADuM1400/ADuM1401/ADuM1402
APPLICATION INFORMATION
PC BOARD LAYOUT
The ADuM140x digital isolator requires no external interface
circuitry for the logic interfaces. Power supply bypassing is
strongly recommended at the input and output supply pins
(Figure 17). Bypass capacitors are most conveniently connected
between Pins 1 and 2 for VDD1 and between Pins 15 and 16 for
VDD2. The capacitor value should be between 0.01 µF and 0.1 µF.
The total lead length between both ends of the capacitor and
the input power supply pin should not exceed 20 mm. Bypass-
ing between Pins 1 and 8 and between Pins 9 and 16 should also
be considered unless the ground pair on each package side is
connected close to the package.
VDD1
GND1
VIA
VIB
VIC/OC
VID/OD
VE1
GND1
VDD2
GND2
VOA
VOB
VOC/IC
VOD/ID
VE2
GND2
Figure 17. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, care
should be taken to ensure that board coupling across the isola-
tion barrier is minimized. Furthermore, the board layout should
be designed such that any coupling that does occur equally
affects all pins on a given component side. Failure to ensure this
could cause voltage differentials between pins exceeding the
device’s Absolute Maximum Ratings, thereby leading to latch-up
or permanent damage.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propaga-
tion delay to a logic low output may differ from the propagation
delay to a logic high.
INPUT (VIX)
OUTPUT (VOX)
tPLH
tPHL
50%
50%
Figure 18. Propagation Delay Parameters
Pulse-width distortion is the maximum difference between
these two propagation delay values and is an indication of how
accurately the input signal’s timing is preserved.
Channel-to-channel matching refers to the maximum that
amount the propagation delay differs between channels within a
single ADuM140x component.
Propagation delay skew refers to the maximum that amount the
propagation delay differs between multiple ADuM140x compo-
nents operating under the same conditions.
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input
cause narrow (~1 ns) pulses to be sent to the decoder via the
transformer. The decoder is bistable and is, therefore, either set
or reset by the pulses, indicating input logic transitions. In the
absence of logic transitions at the input for more than 2 µs, a
periodic set of refresh pulses indicative of the correct input state
are sent to ensure dc correctness at the output. If the decoder
receives no internal pulses of more than about 5 µs, the input
side is assumed to be unpowered or nonfunctional, in which
case the isolator output is forced to a default state (see Table 10)
by the watchdog timer circuit.
The limitation on the ADuM140x’s magnetic field immunity is
set by the condition in which induced voltage in the transformer’s
receiving coil is sufficiently large to either falsely set or reset the
decoder. The following analysis defines the conditions under
which this may occur. The 3 V operating condition of the
ADuM140x is examined because it represents the most
susceptible mode of operation.
The pulses at the transformer output have an amplitude greater than
1.0 V. The decoder has a sensing threshold at about 0.5 V, therefore
establishing a 0.5 V margin in which induced voltages can be toler-
ated. The voltage induced across the receiving coil is given by
V = (–dβ/dt)∑∏rn2; n = 1, 2,…, N
where:
β is magnetic flux density (gauss).
N is the number of turns in the receiving coil.
rn is the radius of the nth turn in the receiving coil (cm).
Given the geometry of the receiving coil in the ADuM140x and
an imposed requirement that the induced voltage be at most
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated as shown in Figure 19.
100.000
10.000
1.000
0.100
0.010
0.001
1k
10k
100k
1M
10M
MAGNETIC FIELD FREQUENCY (Hz)
100M
Figure 19. Maximum Allowable External Magnetic Flux Density
Rev. B | Page 19 of 24
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