SST49LF008A データシートの表示（PDF） - Microchip Technology

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SST49LF008A

8 Mbit Firmware Hub

Microchip Technology 

A Microchip Technology Company

8 Mbit Firmware Hub

SST49LF008A

Write Lock

Data Sheet

The Write-Lock bit, bit 0, controls the lock state described in Table 7. The default Write status of all

blocks after power-up is write locked. When bit 0 of the Block Locking register is set, Program and

Erase operations for the corresponding block are prevented. Clearing the Write-Lock bit will unprotect

the block. The Write-Lock bit must be cleared prior to starting a Program or Erase operation since it is

sampled at the beginning of the operation.

The Write-Lock bit functions in conjunction with the hardware Write Lock pin TBL# for the top Boot

Block. When TBL# is low, it overrides the software locking scheme. The top Boot Block Locking regis-

ter does not indicate the state of the TBL# pin.

The Write-Lock bit functions in conjunction with the hardware WP# pin for blocks 0 to 6. When WP# is

low, it overrides the software locking scheme. The Block Locking register does not indicate the state of

the WP# pin.

Lock Down

The Lock-Down bit, bit 1, controls the Block Locking register as described in Table 7. When in the FWH

interface mode, the default Lock Down status of all blocks upon power-up is not locked down. Once the

Lock-Down bit is set, any future attempted changes to that Block Locking register will be ignored. The

Lock-Down bit is only cleared upon a device reset with RST# or INIT# or power down. Current Lock

Down status of a particular block can be determined by reading the corresponding Lock-Down bit.

Once a block’s Lock-Down bit is set, the Write-Lock bits for that block can no longer be modified, and

the block is locked down in its current state of write accessibility.

JEDEC ID Registers

The JEDEC ID registers for the boot device appear at FFBC0000H and FFBC0001H in the 4 GByte

system memory map, and will appear elsewhere if the device is not the boot device. Register is not

available for read when the device is in Erase/Program operation. Unused register location will read as

00H. Refer to the relevant application note for details. See Table 2 for the device ID code.

©2011 Silicon Storage Technology, Inc.

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