SST49LF008A データシートの表示（PDF） - Microchip Technology

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SST49LF008A

8 Mbit Firmware Hub

Microchip Technology 

A Microchip Technology Company

8 Mbit Firmware Hub

SST49LF008A

Parallel Programming Mode

Data Sheet

Device Operation

Commands are used to initiate the memory operation functions of the device. The data portion of the

software command sequence is latched on the rising edge of WE#. During the software command

sequence the row address is latched on the falling edge of R/C# and the column address is latched on

the rising edge of R/C#.

Reset

A VIL on RST# pin initiates a device reset.

Read

The Read operation of the SST49LF008A device is controlled by OE#. OE# is the output control and is

used to gate data from the output pins. Refer to the Read cycle timing diagram, Figure 13, for further

details.

Byte-Program Operation

The SST49LF008A device is programmed on a byte-by-byte basis. Before programming, one must

ensure that the sector, in which the byte which is being programmed exists, is fully erased. The Byte-

Program operation is initiated by executing a four-byte command load sequence for Software Data

Protection with address (BA) and data in the last byte sequence. During the Byte-Program operation,

the row address (A10-A0) is latched on the falling edge of R/C# and the column Address (A21-A11) is

latched on the rising edge of R/C#. The data bus is latched in the rising edge of WE#. The Program

operation, once initiated, will be completed, within 20 µs. See Figure 14 for Program operation timing

diagram, Figure 17 for timing waveforms, and Figure 25 for its flowchart. During the Program opera-

tion, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the

host is free to perform additional tasks. Any commands written during the internal Program operation

will be ignored.

©2011 Silicon Storage Technology, Inc.

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