SST49LF008A データシートの表示（PDF） - Microchip Technology

部品番号

コンポーネント説明

メーカー

SST49LF008A

8 Mbit Firmware Hub

Microchip Technology 

A Microchip Technology Company

8 Mbit Firmware Hub

SST49LF008A

Data Sheet

Sector-Erase Operation

The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The

sector architecture is based on uniform sector size of 4 KByte. The Sector-Erase operation is initiated

by executing a six-byte command load sequence for Software Data Protection with Sector-Erase com-

mand (30H) and sector address (SA) in the last bus cycle. The internal Erase operation begins after

the sixth WE# pulse. The End-of-Erase can be determined using either Data# Polling or Toggle Bit

methods. See Figure 18 for Sector-Erase timing waveforms. Any commands written during the Sector-

Erase operation will be ignored.

Block-Erase Operation

The Block-Erase Operation allows the system to erase the device in 64 KByte uniform block size for

the SST49LF008A. The Block-Erase operation is initiated by executing a six-byte command load

sequence for Software Data Protection with Block-Erase command (50H) and block address. The

internal Block-Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined

using either Data# Polling or Toggle Bit methods. See Figure 19 for timing waveforms. Any commands

written during the Block-Erase operation will be ignored.

Chip-Erase

The SST49LF008A device provides a Chip-Erase operation only in PP Mode, which allows the user to

erase the entire memory array to the ‘1’s state. This is useful when the entire device must be quickly

erased.

The Chip-Erase operation is initiated by executing a six- byte Software Data Protection command

sequence with Chip-Erase command (10H) with address 5555H in the last byte sequence. The internal

Erase operation begins with the rising edge of the sixth WE#. During the internal Erase operation, the

only valid read is Toggle Bit or Data# Polling. See Table 9 for the command sequence, Figure 20 for

timing diagram, and Figure 28 for the flowchart. Any commands written during the Chip-Erase opera-

tion will be ignored.

©2011 Silicon Storage Technology, Inc.

18

DS25085A

10/11

Share Link: