Data Sheet (Advance Information)
1.4 Block Diagram
Address
Register/
Counter
Figure 1.4 Block Diagram
Program Erase
Controller
HV Generation
ALE
CLE
WE#
CE#
WP#
RE#
Command
Interface
Logic
Command
Register
Data
Register
1024 Mbit + 32 Mbit (1 Gb Device)
X
2048 Mbit + 64 Mbit (2 Gb Device)
D
E
4096 Mbit + 128 Mbit (4 Gb Device)
C
O
D
NAND Flash
E
R
Memory Array
PAGE Buffer
Y Decoder
I/O Buffer
I/O0~I/O7
1.5 Array Organization
Figure 1.5 Array Organization
1024
Blocks
per
Plane
Page Buffer
Plane(s)
0
1
2
1022
1023
2048 bytes
spare bytes
1 Page = (2k + spare) bytes
1 Block = (2k + spare) bytes x 64 pages
= (128k + spare) bytes
1 Plane = (128k + spare) bytes x 1024 Blocks
Note:
For 1 Gb and 2 Gb devices there are 1024 Blocks per Plane
For 4 Gb device there are 2048 Blocks per Plane
2 Gb and 4 Gb devices have two Planes
I/O
[7:0]
Array Organization(x8)
August 3, 2012 S34ML01G2_04G2_01
Spansion® SLC NAND Flash Memory for Embedded
13