S34ML01G200BFI000(2012) データシートの表示（PDF） - Spansion Inc.
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S34ML01G200BFI000 Datasheet PDF : 68 Pages
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Data Sheet (Advance Information)
1.6.3 S34ML04G2
Table 1.5 Address Cycle Map — 4 Gb Device
Bus Cycle
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
1st
A0
A1
A2
A3
A4
A5
A6
A7
2nd
A8
A9
A10
A11
L (1)
L (1)
L (1)
L (1)
3rd
A12
A13
A14
A15
A16
A17
A18
A19
4th
A20
A21
A22
A23
A24
A25
A26
A27
5th
A28
A29
A30
L (1)
L (1)
L (1)
L (1)
L (1)
Notes:
1. L must be set to low.
For the address bits, the following rules apply:
A0 - A11: column address in the page
A12 - A17: page address in the block
A18: plane address (for multiplane operations) / block address (for normal operations)
A19 - A30: block address
1.7 Mode Selection
Table 1.6 Mode Selection
Mode
CLE
ALE
CE#
Read Mode
Command Input
High
Low
Low
Address Input
Low
High
Low
Command Input
High
Low
Low
Program or Erase Mode
Address Input
Low
High
Low
Data Input
Low
Low
Low
Data Output (on going)
Low
Low
Low
Data Output (suspended)
X
X
X
Busy Time in Read
X
X
X
Busy Time in Program
X
X
X
Busy Time in Erase
X
X
X
Write Protect
X
X
X
Stand By
X
X
High
Notes:
1. X can be VIL or VIH. H = Logic level High, L = Logic level Low.
2. WP# should be biased to CMOS high or CMOS low for stand-by mode.
3. During Busy Time in Read, RE# must be held high to prevent unintended data out.
WE#
Rising
Rising
Rising
Rising
Rising
High
High
X
X
X
X
X
RE#
High
High
High
High
High
Falling
High
High (3)
X
X
X
X
WP#
X
X
High
High
High
X
X
X
High
High
Low
0V / VCC (2)
August 3, 2012 S34ML01G2_04G2_01
Spansion® SLC NAND Flash Memory for Embedded
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