QL6250-E データシートの表示（PDF） - QuickLogic Corporation

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QL6250-E

FPGA Combining Performance, Density, and Embedded RAM

QuickLogic Corporation 

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*(at VCC = 2.5 V, TA = 25° C, Worst Case Corner, Speed Grade = -7 (K = 1.16))

The AC Specifications are provided from 7DEOH  to 7DEOH . Logic Cell diagrams and

waveforms are provided from )LJXUH  to )LJXUH .

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tPD

Combinatorial Delay of the longest path: time taken by the combinatorial circuit to

output

- 0.257 ns

tSU

Setup time: time the synchronous input of the flip-flop must be stable before the

active clock edge

0.22 ns

-

tHL

Hold time: time the synchronous input of the flip-flop must be stable after the active

clock edge

0 ns

-

tCO

Clock-to-out delay: the amount of time taken by the flip-flop to output after the

active clock edge.

- 0.255 ns

tCWHI

tCWLO

tSET

Clock High Time: required minimum time the clock stays high

Clock Low Time: required minimum time that the clock stays low

Set Delay: time between when the flip-flop is ”set” (high)

and when the output is consequently “set” (high)

0.46 ns

-

0.46 ns

-

-

0.18 ns



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