QL6250-E データシートの表示（PDF） - QuickLogic Corporation

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QL6250-E

FPGA Combining Performance, Density, and Embedded RAM

QuickLogic Corporation 

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tISU

tIHL

tICO

tIRST

tIESU

tIEH

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Input register setup time: time the synchronous input of the flip-flop must be stable

before the active clock edge

2.50 ns

-

Input register hold time: time the synchronous input of the flip-flop must be stable

after the active clock edge

0 ns

-

Input register clock-to-out: time taken by the flip-flop to output after the active clock

edge

- 1.08 ns

Input register reset delay: time between when the flip-flop is “reset” (low) and when

the output is consequently “reset” (low)

- 0.99 ns

Input register clock enable setup time: time “enable” must be stable before the

active clock edge

0.37 ns

-

Input register clock enable hold time: time “enable” must be stable after the active

clock edge

0 ns

-

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tSID (LVTTL)

tSID (LVCMOS2)

LVTTL input delay: Low Voltage TTL for 3.3 V applications

LVCMOS2 input delay: Low Voltage CMOS for 2.5 V and lower

applications

tSID (LVCMOS18)

tSID (GTL+)

tSID (SSTL3)

tSID (SSTL2)

LVCMOS18 input delay: Low Voltage CMOS for 1.8 V applications

GTL+ input delay: Gunning Transceiver Logic

SSTL3 input delay: Stub Series Terminated Logic for 3.3 V

SSTL2 input delay: Stub Series Terminated Logic for 2.5 V

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- 0.34 ns

- 0.42 ns

-

-

- 0.68 ns

- 0.55 ns

- 0.61 ns

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