IDT72420L12TP データシートの表示（PDF） - Integrated Device Technology

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IDT72420L12TP

CMOS SyncFIFO™ 64 x 8, 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8

Integrated Device Technology 

IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO™

64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8

WCLK

tDS

D0 - D7

tENS

WEN

RCLK

EF

DATA WRITE 1

tENH

tSKEW1

tFRL (1)

tREF

MILITARY AND COMMERCIAL TEMPERATURE RANGES

tDS

tENS

DATA WRITE 2

tENH

tREF

tSKEW1

tFRL (1)

tREF

REN

OE

LOW

Q0 - Q7

tA

DATA IN OUTPUT REGISTER

NOTE:

1. When tSKEW1 ≥ minimum specification, tFRL maximum = tCLK + tSKEW1

When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1

The Latency Timing apply only at the Empty Boundry (EF = LOW).

Figure 7. Empty Flag Timing

DATA READ

2680 drw 09

5.12

12

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