IDT72420L12TP データシートの表示（PDF） - Integrated Device Technology

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IDT72420L12TP

CMOS SyncFIFO™ 64 x 8, 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8

Integrated Device Technology 

IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO™

64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8

tCLKH

tCLKL

WCLK

WEN

tENS

tENH

AF

Full - 8 words in FIFO

(2)

tAF

RCLK

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Full - 7 words in FIFO

tSKEW2 (1)

tAF

tENS

tENH

REN

2680 drw 10

NOTES:

1. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for AF to change during the curent clock cycle. If the time between

the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then AF may not change state until the next WCLK edge.

2. If a write is performed on this rising edge of the write clock, there will be Full - 6 words in the FIFO when AF goes LOW.

Figure 8. Almost Full Flag Timing

5.12

13

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