AT24C16D-PUM データシートの表示（PDF） - Atmel Corporation
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AT24C16D-PUM Datasheet PDF : 28 Pages
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6. Read Operations
Read operations are initiated the same way as Write operations with the exception that the Read/Write Select
bit in the Device Address word must be a Logic 1. There are three Read operations:
Current Address Read
Random Address Read
Sequential Read
6.1 Current Address Read
The internal data word address counter maintains the last address accessed during the last read or write
operation, incremented by one. This address stays valid between operations as long as the VCC is maintained to
the part. The address roll-over during read is from the last byte of the last page to the first byte of the first page
of the memory.
A Current Address Read operation will output data according to the location of the internal data word address
counter. This is initiated with a Start condition, followed by a valid Device Address byte with the R/W bit set to
Logic 1. The device will ACK this sequence and the current address data word is serially clocked out on the
SDA line. All types of Read operations will be terminated if the bus Master does not respond with an ACK (it
NACKs) during the ninth clock cycle, which will force the device into standby mode. After the NACK response,
the Master may send a Stop condition to complete the protocol, or it can send a Start condition to begin the next
sequence.
Figure 6-1. Current Address Read
SCL
12 3 4 567 89 12 345 67 89
SDA
Start
by
Master
Device Address Byte
Data Word (n)
1 0 1 0 A10 A9 A8 1 0 D7 D6 D5 D4 D3 D2 D1 D0 1
MSB
MSB
ACK
from
Slave
NACK
from
Master
Stop
by
Master
6.2 Random Read
A Random Read begins in the same way as a Byte Write operation does to load in a new data word address.
This is known as a “dummy write” sequence; however, the Data Byte and the Stop condition of the Byte Write
must be omitted to prevent the part from entering an internal write cycle. Once the Device Address and Word
Address are clocked in and acknowledged by the EEPROM, the bus Master must generate another Start
condition. The bus Master now initiates a Current Address Read by sending a Start condition, followed by a
valid Device Address byte with the R/W bit set to Logic 1. In this second Device Address byte, the bit positions
usually reserved for the most significant bits of the Word Address (bit 3, 2, and 1) are don’t care bits since the
address that will be read from is determined only by what was sent in the dummy write portion of the sequence.
The EEPROM will ACK the Device Address and serially clock out the data word on the SDA line. All types of
Read operations will be terminated if the bus Master does not respond with an ACK (it NACKs) during the ninth
clock cycle, which will force the device into standby mode. After the NACK response, the Master may send a
Stop condition to complete the protocol, or it can send a Start condition to begin the next sequence.
AT24C16D [DATASHEET] 11
Atmel-8906C-SEEPROM-AT24C16D-Datasheet_052015
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