KSZ9031RNX(2012) データシートの表示（PDF） - Micrel

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KSZ9031RNX
(Rev.:2012)

Gigabit Ethernet Transceiver with RGMII Support

Micrel 

Micrel, Inc.

KSZ9031RNX

Functional Description: 10Base-T/100Base-TX Transceiver

100Base-TX Transmit

The 100Base-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI

conversion, and MLT-3 encoding and transmission.

The circuitry starts with a parallel-to-serial conversion, which converts the RGMII data from the MAC into a 125MHz serial

bit stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized data

is further converted from NRZ-to-NRZI format then transmitted in MLT-3 current output. The output current is set by an

external 12.1kΩ 1% resistor for the 1:1 transformer ratio.

The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude

balance, overshoot, and timing jitter. The wave-shaped 10Base-T output is also incorporated into the 100Base-TX

transmitter.

100Base-TX Receive

The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT-3-to-NRZI conversion, data and

clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.

The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair

cable. Because the amplitude loss and phase distortion are a function of the cable length, the equalizer must adjust its

characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on

comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization. This

is an ongoing process and self-adjusts against environmental changes such as temperature variations.

Next, the equalized signal goes through a DC-restoration and data-conversion block. The DC-restoration circuit

compensates for the effect of baseline wander and improves the dynamic range. The differential data-conversion circuit

converts the MLT-3 format back to NRZI. The slicing threshold is also adaptive.

The clock-recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used

to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/5B

decoder. Finally, the NRZ serial data is converted to the RGMII format and provided as the input data to the MAC.

Scrambler/De-Scrambler (100Base-TX only)

The purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference (EMI)

and baseline wander. Transmitted data is scrambled using an 11-bit wide linear feedback shift register (LFSR). The

scrambler generates a 2047-bit non-repetitive sequence, then the receiver de-scrambles the incoming data stream using

the same sequence as at the transmitter.

10Base-T Transmit

The 10Base-T output drivers are incorporated into the 100Base-TX drivers to allow for transmission with the same

magnetic. The drivers perform internal wave-shaping and pre-emphasis, and output signals with a typical amplitude of

2.5V peak for standard 10Base-T mode and 1.75V peak for energy-efficient 10Base-Te mode. The 10Base-T/10Base-Te

signals have harmonic contents that are at least 31dB below the fundamental frequency when driven by an all-ones

Manchester-encoded signal.

10Base-T Receive

On the receive side, input buffer and level-detecting squelch circuits are used. A differential input receiver circuit and a

phase-locked loop (PLL) perform the decoding function. The Manchester-encoded data stream is separated into clock

signal and NRZ data. A squelch circuit rejects signals with levels less than 300mV or with short pulse widths to prevent

noises at the receive inputs from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks

onto the incoming signal and the KSZ9031RNX decodes a data frame. The receiver clock is maintained active during idle

periods between receiving data frames.

Auto-polarity correction is provided for the receive differential pair to automatically swap and fix the incorrect +/– polarity

wiring in the cabling.

October 2012

17

M9999-103112-1.0

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