KSZ9031RNX データシートの表示（PDF） - Microchip Technology

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KSZ9031RNX

Gigabit Ethernet Transceiver with RGMII Support

Microchip Technology 

KSZ9031RNX

TABLE 2-1: SIGNALS - KSZ9031RNX (CONTINUED)

Pin

Number

Pin

Name

Type

Note

2-1

Description

125 MHz clock output

41

CLK125_NDO/

LED_MODE

I/O

This pin provides a 125 MHz reference clock output option for use by the

MAC.

Config mode: The pull-up/pull-down value is latched as LED_MODE during

power-up/reset. See the Strap-In Options - KSZ9031RNX section for details.

Chip reset (active low)

42

RESET_N

Ipu Hardware pin configurations are strapped-in at the de-assertion (rising edge)

of RESET_N. See the Strap-In Options - KSZ9031RNX section for details.

On-chip 1.2V LDO controller output

43

LDO_O

O

This pin drives the input gate of a P-channel MOSFET to generate 1.2V for

the chip’s core voltages. If the system provides 1.2V and this pin is not used,

it can be left floating.

44

AVDDL_PLL

P

1.2V analog VDD for PLL

45

XO

O

25 MHz crystal feedback

This pin is a no connect if an oscillator or external clock source is used.

46

XI

I

Crystal/Oscillator/External Clock input

25 MHz ±50 ppm tolerance

No connect

47

NC

— This pin is not bonded and can be connected to AVDDH power for footprint

compatibility with the KSZ9021RN Gigabit PHY.

48

ISET

I/O

Set the transmit output level

Connect a 12.1 kΩ 1% resistor to ground on this pin.

Paddle

Note 2-1

P_GND

GND

Exposed paddle on bottom of chip

Connect P_GND to ground.

P = power supply

GND = ground

I = input

O = output

I/O = bi-directional

Ipu = Input with internal pull-up (see Section 6.0, "Electrical Characteristics" for value).

Ipu/O = Input with internal pull-up (see Section 6.0, "Electrical Characteristics" for value) during

power-up/reset; output pin otherwise.

 2016 Microchip Technology Inc.

DS00002117C-page 11

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