LP62S4096E-T データシートの表示（PDF） - AMIC Technology

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LP62S4096E-T

512K X 8 BIT LOW VOLTAGE CMOS SRAM

AMIC Technology 

Block Diagram

A0

A16

A17

A18

I/O1

I/O8

ROW

DECODER

LP62S4096E-T Series

1024 X 4096

MEMORY ARRAY

VCC

GND

INPUT DATA

CIRCUIT

COLUMN I/O

CE1

CE2

CONTROL

OE

CIRCUIT

WE

Pin Description

Symbol

Description

A0 - A18

I/O1 - I/O8

GND

CE1, CE2

OE

WE

VCC

Address Inputs

Data Input/Outputs

Ground

Chip Enable

Output Enable

Write Enable

Power Supply

Recommended DC Operating Conditions

(TA = -25°C to + 85°C)

Symbol

Parameter

Min. Typ. Max. Unit

VCC

GND

Supply Voltage

Ground

2.7 3.0 3.6

V

0

0

0

V

Input High Voltage

VIH

2.2

VCC

-

+ 0.3

V

VIL

Input Low Voltage -0.3

0

+0.6

V

CL

Output Load

-

-

30

pF

TTL Output Load

-

-

1

-

(May, 2010, Version 3.3)

2

AMIC Technology, Corp.

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