LP62S4096E-T データシートの表示（PDF） - AMIC Technology

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LP62S4096E-T

512K X 8 BIT LOW VOLTAGE CMOS SRAM

AMIC Technology 

AC Test Conditions

Input Pulse Levels

Input Rise and Fall Time

Input and Output Timing Reference Levels

Output Load

0.4V to 2.4V

5 ns

1.5V

See Figures 1 and 2

LP62S4096E-T Series

TTL

TTL

CL

30pF

CL

5pF

* Including scope and jig.

* Including scope and jig.

Figure 1. Output Load

Data Retention Characteristics (TA = -25°C to 85°C)

Symbol

Parameter

VDR

VCC for Data Retention

Figure 2. Output Load for tCLZ,

tOHZ, tOL, tCHZ, tWHZ, and tOW

Min. Typ. Max. Unit

Conditions

2.0

-

3.6

V CE1≥ VCC - 0.2V, or

CE2 ≤ 0.2V

ICCDR Data Retention Current

LL-Version

VCC = 2.0V,

-

0.08 3*

μA CE1≥ VCC - 0.2V, or

CE2 ≤ 0.2V

VIN ≤ 0V

tCDR

Chip Disable to Data Retention Time

0

-

-

tR

Operation Recovery Time

tRC

-

-

tVR

VCC Rising Time from Data Retention Voltage to 5

-

-

Operating Voltage

* LP62S4096E-55LLT / 70LLT

ICCDR: max. 1μA at TA = 0°C to + 40°C

ns

ns See Retention Waveform

ms

(May, 2010, Version 3.3)

7

AMIC Technology, Corp.

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