1048EA データシートの表示（PDF） - Lattice Semiconductor
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1048EA Datasheet PDF : 14 Pages
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Specifications ispLSI 1048EA
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TEST 4 #2
COND.
DESCRIPTION1
-170
-125
-100
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
tpd1
A
tpd2
A
fmax (Int.) A
fmax (Ext.) —
fmax (Tog.) —
tsu1
—
1 Data Propagation Delay, 4PT Bypass, ORP Bypass — 5.0 — 7.5 — 10.0 ns
2 Data Propagation Delay, Worst Case Path
— 7.0 — 10.0 — 12.5 ns
3 Clock Frequency with Internal Feedback 3
170 — 125 — 100 — MHz
4
Clock
Frequency
with
External
Feedback
(1
tsu2 +
) tco1
125
— 100
— 77
— MHz
5
Clock
Frequency,
Max.
Toggle
(
1
twh +
twl
)
222 — 167 — 125 — MHz
6 GLB Reg. Setup Time before Clock,4 PT Bypass 3.5 — 4.5 — 6.0 — ns
tco1
A 7 GLB Reg. Clock to Output Delay, ORP Bypass
— 3.5 — 4.5 — 6.0 ns
th1
— 8 GLB Reg. Hold Time after Clock, 4 PT Bypass
0.0 — 0.0 — 0.0 — ns
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
twl
— 9 GLB Reg. Setup Time before Clock
4.5 — 5.5 — 7.0 — ns
— 10 GLB Reg. Clock to Output Delay
— 4.5 — 5.5 — 7.0 ns
— 11 GLB Reg. Hold Time after Clock
0.0 — 0.0 — 0.0 — ns
A 12 Ext. Reset Pin to Output Delay
— 7.0 — 10.0 — 13.5 ns
— 13 Ext. Reset Pulse Duration
4.0 — 5.0 — 6.5 — ns
B 14 Input to Output Enable
— 9.0 — 12.0 — 15.0 ns
C 15 Input to Output Disable
— 9.0 — 12.0 — 15.0 ns
B 16 Global OE Output Enable
— 6.5 — 7.0 — 9.0 ns
C 17 Global OE Output Disable
— 6.5 — 7.0 — 9.0 ns
— 18 External Synchronous Clock Pulse Duration, High 2.25 — 3.0 — 4.0 — ns
— 19 External Synchronous Clock Pulse Duration, Low 2.25 — 3.0 — 4.0 — ns
tsu3
— 20 I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3) 3.0 — 3.0 — 3.5 — ns
th3
— 21 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) 0.0 — 0.0 — 0.0 — ns
1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
Table 2-0030A/1048EA
v.2.0
6
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