1048EA データシートの表示（PDF） - Lattice Semiconductor

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1048EA

In-System Programmable High Density PLD

Lattice Semiconductor 

Specifications ispLSI 1048EA

Internal Timing Parameters1

PARAMETER #

DESCRIPTION

Outputs

tob

50 Output Buffer Delay

tsl

toen

51 Output Slew Limited Delay Adder

52 I/O Cell OE to Output Enabled

todis

53 I/O Cell OE to Output Disabled

tgoe

54 Global OE

Clocks

tgy0

55 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)

tgy1/2

56 Clock Delay, Y1 or Y2 to Global GLB Clock Line

tgcp

57 Clock Delay, Clock GLB to Global GLB Clock Line

tioy2/3

tiocp

58 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line

59 Clock Delay, Clock GLB to I/O Cell Global Clock Line

Global Reset

tgr

60 Global Reset to GLB and I/O Registers

1. Internal timing parameters are not tested and are for reference only.

2. Refer to Timing Model in this data sheet for further details.

-170

-125

-100

UNITS

MIN. MAX. MIN. MAX. MIN. MAX.

— 0.9 — 1.7 — 2.0 ns

— 6.0 — 6.0 — 6.0 ns

— 3.3 — 4.0 — 5.1 ns

— 3.3 — 4.0 — 5.1 ns

— 2.6 — 3.0 — 3.9 ns

0.9 0.9 1.1 1.1 1.9 1.9 ns

0.9 0.9 0.9 0.9 1.5 1.5 ns

0.8 1.8 0.8 1.8 0.8 1.8 ns

0.0 0.0 0.0 0.0 0.0 0.0 ns

0.8 2.8 0.8 2.8 0.8 2.8 ns

— 0.4

— 2.1

— 5.1 ns

Table 2-0037A/1048EA

v.2.0

8

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