ISPLSI1016E(1998) データシートの表示（PDF） - Lattice Semiconductor
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ISPLSI1016E Datasheet PDF : 12 Pages
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Specifications ispLSI 1016E
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER
TEST 4
COND.
#2
DESCRIPTION1
-125
-100
-80
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
tpd1
A 1 Data Prop. Delay, 4PT Bypass, ORP Bypass
– 7.5 – 10.0 – 15.0 ns
tpd2
A 2 Data Prop. Delay, Worst Case Path
– 10.0 – 13.0 – 18.5 ns
fmax
A 3 Clk. Frequency with Int. Feedback3
125 – 100 – 84.0 – MHz
fmax (Ext.)
–
4
Clk.
Frequency
with
Ext.
( Feedback
1
tsu2 +
) tco1
100 – 77.0 – 57.0 – MHz
fmax (Tog.)
–
5
Clk.
Frequency,
Max.
Toggle(
1
twh +
) tw1
167 – 125 – 100 – MHz
tsu1
– 6 GLB Reg. Setup Time before Clk., 4 PT Bypass 5.0 – 7.0 – 8.5 – ns
tco1
A 7 GLB Reg. Clk. to Output Delay, ORP Bypass
– 4.5 – 5.0 – 8.0 ns
th1
– 8 GLB Reg. Hold Time after Clk., 4 PT Bypass
0.0 – 0.0 – 0.0 – ns
tsu2
– 9 GLB Reg. Setup Time before Clk.
5.5 – 8.0 – 9.5 – ns
tco2
– 10 GLB Reg. Clk. to Output Delay
– 5.5 – 6.0 – 9.5 ns
th2
– 11 GLB Reg. Hold Time after Clk.
0.0 – 0.0 – 0.0 – ns
tr1
A 12 Ext. Reset Pin to Output Delay
– 10.0 – 13.5 – 17.0 ns
trw1
– 13 Ext. Reset Pulse Duration
5.0 – 6.5 – 10.0 –
ns
tptoeen
B 14 Input to Output Enable
– 12.0 – 15.0 – 20.0 ns
tptoedis
C 15 Input to Output Disable
– 12.0 – 15.0 – 20.0 ns
tgoeen
B 16 Global OE Output Enable
– 7.0 – 9.0 – 10.5 ns
tgoedis
C 17 Global OE Output Disable
– 7.0 – 9.0 – 10.5 ns
twh
– 18 Ext. Sync. Clk. Pulse Duration, High
3.0 – 4.0 – 5.0 –
ns
twl
– 19 Ext. Sync. Clk. Pulse Duration, Low
3.0 – 4.0 – 5.0 –
ns
tsu3
– 20 I/O Reg. Setup Time before Ext. Sync. Clk. (Y2, Y3) 3.0 – 3.5 – 4.5 –
ns
th3
– 21 I/O Reg. Hold Time after Ext. Sync. Clk. (Y2, Y3) 0.0 – 0.0 – 0.0 –
ns
1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions Section.
Table 2-0030-16/125,100, 80
5
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