AN2125 データシートの表示（PDF） - STMicroelectronics

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uPSD3300 Series Design Guide for DK3300-ELCD Using KEIL

STMicroelectronics 

uPSD3300 Series Design Guide for DK3300-ELCD Using KEIL

1.1 uPSD3300 Family Overview

The uPSD3300 family is a turbo 4-clock per instruction 8032 MCU capable of being clocked

up to 40MHz at 3.3V or 5.0V at industrial operating temperature range. Currently there are

twelve family members that contain different combinations of flash memory size, operating

voltage, and packaging (please see the full datasheet). In this Application Note, uPSD3334D-

40U6 is used as the example. The term "Turbo uPSD" is used throughout the remainder of the

document for brevity (see the Turbo uPSD3334 block diagram shown in Figure 2).

The Turbo uPSD family has a unique memory structure that includes two independent flash

memory arrays (Main and Secondary) capable of read-while-write operation. This is ideal for

In-Application Programming (IAP) because the 8032 can fetch instructions from one flash ar-

ray while erasing/writing the other array. Individual sectors of each flash memory array can be

mapped to virtually any 8032 address by the Decode PLD (DPLD) for total flexibility. The Turbo

uPSD also contains a Page Register whose outputs feed the inputs of the DPLD. This allows

paging (or banking) of flash memory to break the 8032's inherent limit of 64 Kbyte addresses.

The 8032 may write to the Page Register at runtime.

For more complex designs, the Turbo uPSD is capable of placing each of the flash memory

arrays (Main or Secondary) into 8032 code address space, into 8032 data space, or into both

code and data space on the fly. Mapping flexibility like this supports IAP because either flash

array may be temporarily placed into data space while the firmware is updated, then moved

back into code space when finished, all under control of the 8032.

Many peripherals are available in this Turbo uPSD, including: two UART channels, one IrDA

channel, one SPI channel, one I2C channel, six PWM channels, eight 10-bit ADC channels,

nine Timer/Counters, a watchdog timer, low-VCC detection with reset-out, a general purpose

PLD, many GPIO and a USB-JTAG Debugger.

All of the peripherals on Ports 1, 3, and 4 are controlled using 8032 Special Function Registers

(SFRs).

I/O Signals on ports A, B, C, and D are controlled one of two ways:

1. by a block of xdata memory mapped control registers, whose base address (csiop) can be

mapped anywhere using the DPLD; and

2. by the programmable logic.

In addition, Turbo uPSD offers a Cross-Bar I/O, which means that Peripheral functions on Port

1 are also available on Port 4 (cross-bar switch), providing more flexibility. There is no need to

sacrifice one peripheral function when two functions are available on a single pin, just use the

other port.

The JTAG channel on Port C is used for ISP and debug of the 8032 MCU core. ISP is ideal for

rapid code iterations during firmware development and for Just-In-Time inventory manage-

ment during manufacturing. JTAG ISP eliminates the need for sockets and pre-programmed

devices, and requires no participation of the 8032. JTAG debug eliminates the need for expen-

sive and intrusive hardware In-Circuit Emulator (ICE).

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