GS84118AB-133I データシートの表示（PDF） - Giga Semiconductor

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GS84118AB-133I

256K x 18 Sync Cache Tag

Giga Semiconductor 

Write Cycle Timing

GS84118AT/B-166/150/130/100

CLK

ADSP

ADSC

ADV

A0–A17

GW

BWE

BW1–

BW2

CE1

CE2

CE3

Single Write

Burst Write

Write

Deselected

tS tH

tS tH

tKH tKL tKC ADSP is blocked by CE1 inactive

ADSC initiated write

tS tH

tS tH ADV must be inactive for ADSP Write

WR1

WR2

WR3

tS tH

tS tH

tS tH

WWR1

tS tH

tS tH

WWRR22

CE1 masks ADSP

tS tH

CE2 and CE3 only sampled with ADSP or ADSC

WWRR33

Deselected with CE2

OE

DQ1–16 Hi-Z

DQP1–2

DE

tS tH

D1a

tS tH

Write specified byte for 2a and all bytes for 2b, 2c& 2d

D2a

D2b

D2c

D2d

D3a

Rev: 1.00 9/2002

13/27

© 2002, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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