GS84118AB-133I データシートの表示（PDF） - Giga Semiconductor

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GS84118AB-133I

256K x 18 Sync Cache Tag

Giga Semiconductor 

Pipeline—Read Cycle Timing

GS84118AT/B-166/150/130/100

CLK

ADSP

ADSC

ADV

A0–A17

GW

BWE

BW1–

BW4

CE1

CE2

CE3

OE

DQ1–16

DQP1–2

Single Read

Burst Read

tS tH

tKH

tKC

tKL

ADSP is blocked by CE1 inactive

tS tH

ADSC initiated read

tS tH

Suspend Burst

tS tH

RD1

RD2

tS

RD3

tH

tS

tH

tS tH

CE1 masks ADSP

tS tH

CE2 and CE3 only sampled with ADSP or ADSC

tS tH

tOE

tOLZ

tOHZ

tKQX

Hi-Z

Q1a

Q2a Q2b

Q2c

tLZ

tKQ

Deselected with CE2

tKQX

Q2d

Q3a

tHZ

Rev: 1.00 9/2002

16/27

© 2002, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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