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A42MX36-PG100A データシートの表示(PDF) - Microsemi Corporation

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A42MX36-PG100A
Microsemi
Microsemi Corporation Microsemi
A42MX36-PG100A Datasheet PDF : 173 Pages
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40MX and 42MX FPGAs
3 40MX and 42MX FPGAs
3.1
3.2
3.2.1
General Description
Microsemi's 40MX and 42MX families offer a cost-effective design solution at 5V. The MX devices are
single-chip solutions and provide high performance while shortening the system design and development
cycle. MX devices can integrate and consolidate logic implemented in multiple programmable array
logics (PALs), complex programmable logic devices (CPLDs), and FPGAs. Example applications include
high-speed controllers and address decoding, peripheral bus interfaces, digital signal processor (DSP),
and co-processor functions.
The MX device architecture is based on Microsemi’s patented antifuse technology implemented in a
0.45µm triple-metal CMOS process. With capacities ranging from 3,000 to 54,000 system gates,
the MX devices provide performance up to 250 MHz, are live on power-up and have one-fifth the standby
power consumption of comparable FPGAs. MX FPGAs provide up to 202 user I/Os and are available in a
wide variety of packages and speed grades.
A42MX24 and A42MX36 devices also feature multiPlex I/Os, which support mixed-voltage systems,
enable programmable peripheral component interconnect (PCI), deliver high-performance operation at
both 5.0V and 3.3V, and provide a low-power mode. The devices are fully compliant with the PCI local
bus specification
(version 2.1). They deliver 200 MHz on-chip operation and 6.1 ns clock-to-output performance.
The 42MX24 and 42MX36 devices include system-level features such as
IEEE Standard 1149.1 (JTAG) Boundary Scan Testing and fast wide-decode modules. In addition, the
A42MX36 device offers dual-port SRAM for implementing fast first in first out (FIFOs), last in first out
(LIFOs), and temporary data storage. The storage elements can efficiently address applications requiring
wide data path manipulation and can perform transformation functions such as those required for
telecommunications, networking, and DSP.
All MX devices are fully tested over automotive and military temperature ranges. In addition, the largest
member of the family, the A42MX36, is available in both CQ208 and CQ256 ceramic packages screened
to MIL-STD-883 levels. For easy prototyping and conversion from plastic to ceramic, the CQ208 and
PQ208 devices are pin-compatible.
MX Architectural Overview
The MX devices are composed of fine-grained building blocks that enable fast, efficient logic designs. All
devices within these families are composed of logic modules, I/O modules, routing resources and clock
networks, which are the building blocks for fast logic designs. In addition, the A42MX36 device contains
embedded dual-port SRAM modules, which are optimized for high-speed data path functions such as
FIFOs, LIFOs and scratch pad memory. A42MX24 and A42MX36 also contain wide-decode modules.
Logic Modules
The 40MX logic module is an eight-input, one-output logic circuit designed to implement a wide range of
logic functions with efficient use of interconnect routing resources.(see the following figures).
The logic module can implement the four basic logic functions (NAND, AND, OR and NOR) in gates of
two, three, or four inputs. The logic module can also implement a variety of D-latches, exclusivity
functions, AND-ORs and OR-ANDs. No dedicated hard-wired latches or flip-flops are required in the
array; latches and flip-flops can be constructed from logic modules whenever required in the application.
DS2316 Datasheet Revision 16.0
8

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