MAR281F データシートの表示（PDF） - Dynex Semiconductor
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MAR281F Datasheet PDF : 55 Pages
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MAS281
Label
MAIN
Cycle
B1
P
B1
B1
P
B1
P
B1
P
B1
P
B1
P
P
B2
P
I/O
P
B2
P
B2
P
B2
P
B1
P
B1
B1
P
B1
B2
M
M
BPU
P
P
I/O
MMU
P
P
P
P
P
I/O
I/O
P
P
B2
1. Enable Control of DMAE Output signal
2. -
3. Clear MAS281 Execution Unit Status Word (SW)
Clear Interrupt Mask (MK) (Internal l/O command, SKM 2000H)
4. Clear Pending Interrupt Register (Pl) and Fault Register (FT) (Internal l/O Command, CLIR,2001 H)
Clear Instruction Counter (IC)
5. -
6. Disable Interrupts (Internal l/O Command, DSBL,2003H)
7. -
8. Clear MMU Status Word (Internal l/O Command, WSW, 200EH) (Note 1)
9. -
10. Disable DMA Access (lnternal l/O Command, DMAD, 4007H)
11. -
12. Read Configuration Register (Internal l/O Command, RCW, 8400H, CONFWN Drops low per Figure 25,
Section 5.0)
13. -
14. -
15. - (If Output Discrete Register Present, then Continue; Else, Skip to 18.)
(16). -
(17). Clear Output Discrete Register (External l/O Command)
18. -
19. - (If BPU present, then Branch to BPU; else, continue)
20. -
21. - (If MMU present, then Branch to MMU, Else, Continue)
22. - (Setup Temporary Register to indicate No MMU Present)
23. - (Branch to MAS281 BIT)
24. -
25 Enable Start-Up ROM (Internal l/O Command, ESUR,4004H; SURE Raises High per Figure 25,
Section 5.0)
26. -
27. Clear and Start Timer A (Internal l/O Command, OTA,400AH)
28. Reset the Trigger-Go timer (mternal l/O Command, GO,400BH)
29. -
30. Clear and Start Timer B (Internal l/O Command, OTB,400EH)
31. - (Branch to Load Instruction Pipeline Routine)
32. Load data-ln register (Dl) and instruction Register A (IA) from [IC] Increment IC
33. Load Data-ln Register (Dl) and Instruction Register a (IA) from [IC] ([lA] Moves to IB), Increment IC,
Map Instruction Register B (IB) into Mlcrocode Routine
(1). -
(2). - (Set Loop to Clear Memory Protect RAM)
(3). Clear a Location in MPRAM (Internal l/O Command, LMP,50XXH), Increment Address, Do 128 Times
(4). - (Branch Back to 20 )
(1). -
(2). -
(3). - (Setup Loop to Load Instructlon Page Registers (IPR) and Operand Page Registers (OPR) with
Sequential Values of 0 to 255)
(4). -
(5). -
(6). Load a Location in the IPR wlth the value of the Location Address (Internal l/O Command, WIPR,
51 XYH)
(7). Load a Location in the OPR Increment Loaded Value with the Value of the Location Address (Internal
I/O Command. WOPR,52XYH)
(8). - (Increment IPR Address)
(9). - (Increment OPR Address- Repeat Loop 14 - 9 1256 Times)
(10). - (Setup Temporary Register to Indlcate MMU Present; Branch back to 23)
Notes:
1.
2.
3.
4.
This operation is performed whether or not an MMU is present.
“-” indicates internal CPU operation
Sequence numbers in “( )” are performed only under the stated conditions.
Each step enumerated above represents a single machine (SYNC) cycle of the type shown in the “Cycle” column.
“P” indicates a 5 OSC cycle,60% duty cycle, machine cycle.
“I/O” and “M” Indicate a 5 OSC cycle,50% duty cycle, machine cycle.
“B1” indicates a 6 OSC cycle 50% duty cycle machine cycle.
“B2” indicates a 6 OSC cycle 66% duty cycle machine cycle
Table 3: MAS281 Initialisation Sequence
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