M29W008B データシートの表示（PDF） - STMicroelectronics
部品番号
コンポーネント説明
メーカー
M29W008B Datasheet PDF : 30 Pages
| |||
M29W008T, M29W008B
Table 15A. Write AC Characteristics, Write Enable Controlled
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
M29W008T / M29W008B
Symbol Alt
Parameter
-90
VCC = 3.0V to 3.6V
CL = 30pF
-100
VCC = 2.7V to 3.6V
CL = 30pF
Min
Max
Min
Max
tAVAV
tWC Address Valid to Next Address Valid
90
100
tELWL
tCS Chip Enable Low to Write Enable Low
0
0
tWLWH
tWP Write Enable Low to Write Enable High
45
50
tDVWH
tDS Input Valid to Write Enable High
45
50
tWHDX
tDH Write Enable High to Input Transition
0
0
tWHEH
tCH Write Enable High to Chip Enable High
0
0
tWHWL tWPH Write Enable High to Write Enable Low
30
30
tAVWL
tAS Address Valid to Write Enable Low
0
0
tWLAX
tAH Write Enable Low to Address Transition
45
50
tGHWL
Output Enable High to Write Enable Low
0
0
tVCHEL tVCS VCC High to Chip Enable Low
50
50
tWHGL tOEH Write Enable High to Output Enable Low
0
0
tPHPHH (1,2) tVIDR RP Rise Time to VID
500
500
tPLPX
tRP RP Pulse Width
tWHRL (1) tBUSY Program Erase Valid to RB Delay
tPHWL (1) tRSP RP High to Write Enable Low
Notes: 1. Sample only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.
500
500
90
90
4
4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
µs
Block Erase (BE) Instruction. This instruction
uses a minimum of six write cycles. The Erase
Set-up command 80h is written to address 5555h
on third cycle after the two Coded cycles. The Block
Erase Confirm command 30h is similarly written on
the sixth cycle after another two Coded cycles.
During the input of the second command an ad-
dress within the block to be erased is given and
latched into the memory. Additional block Erase
Confirm commands and block addresses can be
written subsequently to erase other blocks in par-
allel, without further Coded cycles. The erase will
start after the erase timeout period (see Erase
Timer Bit DQ3 description). Thus, additional Erase
Confirm commands for other blocks must be given
within this delay. The input of a new Erase Confirm
command will restart the timeout period. The status
of the internal timer can be monitored through the
level of DQ3, if DQ3 is ’0’ the Block Erase Com-
mand has been given and the timeout is running, if
DQ3 is ’1’, the timeout has expired and the P/E.C.
is erasing the Block(s). If the second command
given is not an erase confirm or if the Coded cycles
are wrong, the instruction aborts, and the device is
reset to Read Array. It is not necessary to program
the block with 00h as the P/E.C. will do this auto-
matically before to erasing to FFh. Read operations
after the sixth rising edge of W or E output the
status register status bits.
18/30
Share Link: 