PM4541 データシートの表示（PDF） - PMC-Sierra

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PM4541

T1XC EVALUATION DAUGHTER BOARD

PMC-Sierra 

TELECOM STANDARD PRODUCT

PMC-920314

ISSUE 2

PMC-Sierra, Inc.

PM4541 T1XC-EVBD

T1XC EVALUATION DAUGHTERBOARD

3.2.1 External Signal Header

This header is provided to accept an external clock and framing pulse source. These

inputs are then buffered for use on the board. External clock sources must be

buffered through this header to avoid possible damage to the T1XCs or DPLL.

Signal

EXTFP

EXTCLK

BEXTFP

BEXTCLK

Type

I

I

O

O

Ref.

J26-2

J26-4

J27-1

J27-2

Description

External Framing Pulse Input

External Clock Input

Buffered External Framing Pulse

Buffered External Clock

3.2.2 DPLL Header

This header is provided to give access to the clock generating MT8940 DPLL chip

as well as provide direct oscillator access. All of the major DPLL outputs are brought

out to this header even though they may be of limited use with the T1XC (e.g. the

4.096 MHz clock).

Signal

FPIN

C8KB

GFP

C1M5

C1M5B

C2M

C2MB

C4M

Type Ref.

I J29-2

I/O J29-1

I/O J29-3

O J29-4

O J29-5

O J29-6

O J29-7

O J29-8

Description

1.544 MHz Framing pulse input to MT8940.

2.048 MHz Framing pulse in/out (mode dependent).

8 kHz Framing pulse output from the MT8940. Note

that this active low output signal is derived from the

16.388 MHz clock and has a 244ns pulsewidth. This

frame pulse signal signal should only be routed to

the T1XC when the backplane is configured for

2.048 MHz; this signal is not suitable when the

T1XC backplane is 1.544 MHz.

1.544 MHz Output clock from MT8940.

Inverted C1M5 clock.

2.048 MHz output clock from MT8940.

Inverted C2M clock.

4.096 MHz Output clock from MT8940.

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