5962F9563501QXC データシートの表示（PDF） - Intersil
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5962F9563501QXC Datasheet PDF : 36 Pages
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HS-RTX2010RH
CR
1514 1312 1110 9 8 7 6 5 4 3 2 1 0
R/W; CARRY
R/W; COMPLEX CARRY
R/W; BYTE ORDER BIT
RESETS TO 0. MODES:
1 = ADDRESSING MODE 1
0 = ADDRESSING MODE 0
R/W; BOOT
DRIVES OUTPUT SIGNAL
TO SELECT BOOT ROM;
WRITE - ONLY (READS AS 0);
SET INTERRUPT DISABLE;
0 = INT. ENABLED;
1 = INT. DISABLED
RESERVED (NOTE)
NMI MODE
1 = RETURN FROM NMI POSSIBLE
0 = NO RETURN FROM NMI
(RTX 2000 MODE)
RESERVED (NOTE)
ARCE; ASIC READ CYCLE EXTEND
WHEN SET EXTENDS CYCLE ON
EXTERNAL ASIC READS
READ ONLY; INTERRUPT
DISABLE STATUS
READ ONLY;
INTERRUPT LATCH
NOTE: Always read as ‘‘0’’. Should be set = 0 during Write operations.
FIGURE 11. CR BIT ASSIGNMENTS
PC : The Program Counter Register contains the address
of the next instruction to be fetched from Main Memory. At
RESET, the contents of PC are set to 0.
I : The Index Register contains 16 bits of the 21-bit top
element of the Return Stack, and is also used to hold the
count for streamed and loop instructions (see Figure 19). In
addition, I can be used to hold data and can be written
from TOP . The contents of I may be accessed in
either the push/pop mode in which values are moved to/from
stack memory as required, or in the read/write mode in
which the stack memory is not affected. The ASIC address
used for I determines what type of operation will be
performed (see Table 5). When the Streamed Instruction
Mode (see RTX Programmer’s Reference Manual) is used, a
count is written to I and the next instruction is executed
that number of times plus one (i.e., count + 1).
MD : The Multi-Step Divide Register holds the divisor
during Step Divide operations, while the 32-bit dividend is in
TOP and EXT. MD may also be used as a general
purpose scratch pad register.
SR : The Square Root Register holds the intermediate
values used during Step Square Root calculations. SR
may also be used as a general purpose scratch pad register.
On-Chip Peripheral Registers
The HS-RTX2010RH has an on-chip Interrupt Controller, a
Memory Page Controller, two Stack Controllers, three
Timer/Counters, a Multiplier-Accumulator, a Barrel Shifter,
and a Leading Zero Detector. Each of these peripherals
utilizes on-chip registers to perform its functions.
Timer/Counter Registers
TC0 , TC1 , TC2 : The Timer/Counter Registers are
16-bit read-only registers which contain the current count
value for each of the three Timer/Counters. The counter is
decremented at each rising clock edge of TCLK. Reading
from these registers at any time does not disturb their
contents. The sequence of Timer/Counter operations is
shown in Figure 23 in the Timer/Counters section.
TP0 , TP1 , TP2 : The Timer Preload Registers are
write-only registers which contain the initial 16-bit count
values which are written to each timer. After a timer counts
down to zero, the preload register for that timer reloads its
initial count value to that timer register at the next rising clock
edge, synchronously with TCLK. Writing to these registers
causes the count to be loaded into the corresponding Timer/
Counter register on the following cycle.
Multiplier-Accumulator (MAC) Registers:
MHR : The Multiplier High Product Register holds the most
significant 16 bits of the 32-bit product generated by the RTX
Multiplier. If the IBC register’s ROUND bit is set, this
register contains the rounded 16-bit output of the multiplier.
In the Accumulator context, this register holds the middle 16
bits of the MAC.
MLR : The Multiplier Lower Product Register holds the least
significant 16 bits of the 32-bit product generated by the RTX
Multiplier. It is also the register which holds the least
significant 16 bits of the MAC Accumulator.
MXR : The MAC Extension Register holds the most significant
16 bits of the MAC Accumulator. When using the Barrel Shifter,
this register holds the shift count. When using the Leading Zero
Detector, the leading zero count is stored in this register.
Interrupt Controller Registers
IVR : The Interrupt Vector Register is a read-only register
which holds the current Interrupt Vector value. See Figure 12
and Table 4.
IBC BIT 15
IBC BIT 14
IBC BIT 13
IBC BIT 12
IBC BIT 11
IBC BIT 10
VECTOR ADDRESS
(SEE TABLE 1)
ALL ZEROS
15 14 13 12 11 10 9 8 7 6 5 4 3 2 I1BC0 IVR
MA15-MA00
FIGURE 12. IVR BIT ASSIGNMENTS
IBC : The Interrupt Base/Control Register is used to store
the Interrupt Vector base address and to specify
configuration information for the processor, as indicated by
the bit assignments in Figure 13.
12
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