5962F9563501QXC データシートの表示（PDF） - Intersil
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5962F9563501QXC Datasheet PDF : 36 Pages
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HS-RTX2010RH
Substacks
Each 256-word stack may be subdivided into up to eight 32
word substacks, four 64 word substacks, or two 128 word
substacks. This is accomplished under hardware control for
simplified management of multiple tasks. Stack size is
selected by writing to bits 1 and 2 of the SUR for the
Parameter Stack, and bits 9 and 10 for the Return Stack.
Substacks are implemented by making bits 5-7 of the SPR
(for the Parameter Stack) and bits 13-15 of the SPR (for the
Return Stack) control bits. For example, if there were eight
32 word substacks implemented in the Parameter Stack, bits
5-7 of the SPR are not incremented, but instead are used
as an offset pointer into the Parameter Stack to indicate the
beginning point (i.e., sub stack number) of each 32 word
substack implemented. Because of this, a particular
substack is selected by writing a value which contains both
the stack pointer value and the substack number to the
SPR .
Each stack has a Stack Start Flag (PSF and RSF) which
may be used for implementing virtual stacks. For the
Parameter Stack, the Start Flag is bit zero of the SUR , and
for the Return Stack it is bit eight. If the Stack Start Flag is
one, the stack starts at the bottom of the stack or substack
(location 0). If the Stack Start Flag is zero, the substack
starts in the middle of the stack. An exception to this occurs
if the overflow limit in SVR is set for a location below the
middle of the stack. In this case, the stacks always start at
the bottom locations. See Table 2 for the possible stack
configurations. Manipulating the Stack Start Flag provides a
mechanism for creating a virtual stack in memory which is
maintained by interrupt driven handlers.
Possible applications for substacks include use as a
recirculating buffer (to allow quick access for a series of
repeated values such as coefficients for polynomial
evaluation or a digital filter), or to log a continuous stream of
data until a triggering event (for analysis of data before and
after the trigger without having to store all of the incoming
data). The latter application could be used in a digital
oscilloscope or logic analyzer.
Stack Error Conditions
Stack errors include overflow, underflow, and fatal errors.
Overflows occur when an attempt is made to push data onto
a full stack. Since the stacks wrap around, the result is that
existing data on the stack will be overwritten by the new data
when an overflow occurs. Underflows occur when an attempt
is made to pop data off an empty stack, causing invalid data
to be read from the stack. In both cases, a buffer zone may
be set up by initializing SVR and SUR so that stack error
interrupts are generated prior to an actual overflow or
underflow. The limits may be determined from the contents
of SVR and SUR using Table 2. The state of all stack
errors may be determined by examining the five least
significant bits of IBC , where the stack error flags may be
read but not written to. All stack error flags are cleared
whenever a new value is written to SPR .
Fatal Stack Error: Each stack can also experience a fatal
stack error. This error condition occurs when an attempt is
made to push data onto or to pop data off of the highest
location of the substack. It does not generate an interrupt
(since the normal stack limits can be used to generate the
interrupt). The fatal errors for the stacks are logically OR’ed
together to produce bit 0 of the Interrupt Base Control
Register, and they are cleared whenever SPR is written to.
The implication of a fatal error is that data on the stack may
have been corrupted or that invalid data may have been read
from the stack.
HS-RTX2010RH Timer/Counters
The HS-RTX2010RH has three 16-bit timers, each of which
can be configured to perform timing or event counting. All
decrement synchronously with the rising edge of TCLK.
Timer registers are readable in a single machine cycle.
The timer selection bits of the IBC determine whether a
timer is to be configured for external event counting or
internal time-base timing. This configures the respective
counter clock inputs to the on-chip TCLK signal for internal
timing, or to the EI5 - EI3 input pins for external signal event
counting. EI5, EI4, and EI3 are synchronized internally with
TCLK. See Table 3 for Timer/Clock selection by IBC bit
values.
The timers ( TC0 , TC1 and TC2 ) are all free-running,
and when they time out, they reload automatically with the
programmed initial value from their respective Timer Pre
load Registers ( TPO → TC0 , TP1 → TC1 , and TP2
→ TC2 ), then continue timing or counting.
Each timer provides an output to the Interrupt Controller to
indicate when a time-out for the timer has occurred.
The HS-RTX2010RH can determine the state of a timer at
any time either by reading the timer’s value, or upon a time-
out by using the timer’s interrupt (see the Interrupt Controller
section for more information about how timer interrupts are
handled). Figure 23 shows the sequence of Timer/Counter
operations.
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