5962F9563501QXC データシートの表示（PDF） - Intersil
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5962F9563501QXC Datasheet PDF : 36 Pages
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HS-RTX2010RH
SUR
15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0
PSF: PARAMETER STACK
START FLAG
PARAMETER SUBSTACK BITS:
= 00: EIGHT 32 WORD STACKS
= 01: FOUR 64 WORD STACKS
= 10: TWO 128 WORD STACKS
= 11: ONE 256 WORD STACK
PSU: PARAMETER
STACK UNDERFLOW LIMIT
0 - 31 WORDS FROM
BOTTOM OF SUBSTACK
RSF: RETURN STACK
START FLAG
RETURN SUBSTACK BITS:
= 00: EIGHT 32 WORD STACKS
= 01: FOUR 64 WORD STACKS
= 10: TWO 128 WORD STACKS
= 11: ONE 256 WORD STACK
RSU: RETURN STACK
UNDERFLOW LIMIT
0 - 31 WORDS FROM
BOTTOM OF SUBSTACK
FIGURE 17. SUR BIT ASSIGNMENTS
Memory Page Controller Registers
CPR : The Code Page Register contains the value for the
current 32K-word Code page. See Figure 18 for bit field
assignments.
CPR
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
(NOTE)
MA19
MA18
MA17
MA16
NOTE: Always read as ‘‘0’’. Should be set = 0 during Write operations.
FIGURE 18. CPR BIT ASSIGNMENTS
IPR : The Index Page Register extends the Index Register
( I ) by 5 bits; i.e., when a Subroutine Return is performed,
the IPR contains the Code page from which the subroutine
was called, and comprises the 5 most significant bits of the
top element of the Return Stack. See Figure 19. During
nonsubroutine operation, writing to I causes the current
Code page value to be written to IPR . Reading or writing
directly to IPR does not push the Return Stack.
DPR : The Data Page Register contains the value for the
current 32K-word Data page. See Figure 20 for bit field
assignments.
UPR : The User Page Register contains the value for the
current User page. See Figure 21 for bit field assignments.
UBR : The User Base Address Register contains the base
address for User Memory Instructions. See Figure 21 for bit
field assignments.
14
BIT ASSIGNMENTS DURING SUBROUTINE OPERATIONS
IPR
I
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TYPE OF RETURN
= 1: INTERRUPT RETURNS:
= 0: SUBROUTINE RETURNS:
DEFINES RETURN ADDRESS
WHERE DPRSEL BIT IS
STORED DURING INTERRUPT
OR SUBROUTINE CALL
BIT ASSIGNMENTS DURING NON-SUBROUTINE OPERATIONS
IPR
I
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USED FOR TEMPORARY
STORAGE OF VARIABLES,
LOOP COUNTS, AND
STREAM COUNTS
CURRENT CODE
PAGE VALUE
FIGURE 19. I AND IPR BIT ASSIGNMENTS
DPR
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
(NOTE)
MA19
MA18
MA17
MA16
NOTE: Always read as ‘‘0’’. Should be set = 0 during Write operations.
FIGURE 20. DPR BIT ASSIGNMENTS
USER PAGE
REGISTER
RESERVED
(NOTE)
MA19
MA18
MA17
MA16
USER BASE
ADDRESS
REGISTER
UPR
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UBR
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA15 - MA06
MA05
MA04
MA03
MA02
MA01
NOT USED TO GENERATE
THIS ADDRESS
INSTRUCTION 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGISTER
IR
NOTE: Always read as ‘‘0’’. Should be set = 0 during Write operations.
FIGURE 21. UPR AND UBR BIT ASSIGNMENTS
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