HMS30C7202N データシートの表示（PDF） - MagnaChip Semiconductor
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HMS30C7202N Datasheet PDF : 179 Pages
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HMS30C7202N
10.7 TIMER ............................................................................................................................................................. 127
10.7.1 External Signals ....................................................................................................................................... 127
10.7.2 Registers................................................................................................................................................... 127
10.7.2.1 Timer [0,1,2] Base Register (T[0,1,2]BASE) ................................................................................... 127
10.7.2.2 Timer [0,1,2] Count Register (T[0,1,2]COUNT).............................................................................. 128
10.7.2.3 Timer [0,1,2] Control Register (T[0,1,2]CTRL)............................................................................... 128
10.7.2.4 Timer Top-level Control Register (TOPCTRL)................................................................................ 128
10.7.2.5 Timer Status Register (TOPSTAT) ................................................................................................... 129
10.7.2.6 Timer Lower 32-bit Count Register of 64-bit Counter (T64LOW) .................................................. 129
10.7.2.7 Timer Upper 32-bit Count Register of 64-bit Counter (T64HIGH).................................................. 129
10.7.2.8 Timer 64-bit Counter Control Register (T64CTRL)......................................................................... 129
10.7.2.9 Timer 64-bit Counter Test Register (T64TR) ................................................................................... 129
10.7.2.10 Timer Lower 32-bit Base Register of 64-bit Counter (T64LBASE)................................................. 130
10.7.2.11 Timer Upper 32-bit Base Register of 64-bit Counter (T64HBASE)................................................. 130
10.7.2.12 PWM Channel [0,1] Count Register (P[0,1]COUNT)...................................................................... 130
10.7.2.13 PWM Channel [0,1] Width Register (P[0,1]WIDTH) ...................................................................... 131
10.7.2.14 PWM Channel [0,1] Period Register (P[0,1]PERIOD) .................................................................... 131
10.7.2.15 PWM Channel [0,1] Control Register (P[0,1]CTRL)....................................................................... 131
10.7.2.16 PWM Channel[0,1] Test Register(P[0,1]PWMTR) .......................................................................... 131
10.8 UART/SIR........................................................................................................................................................ 132
10.8.1 External Signals ....................................................................................................................................... 132
10.8.2 Registers................................................................................................................................................... 133
10.8.2.1 RBR/THR/DLL ................................................................................................................................ 134
10.8.2.2 IER/DLM ......................................................................................................................................... 134
10.8.2.3 IIR/FCR............................................................................................................................................ 134
10.8.2.4 LCR .................................................................................................................................................. 136
10.8.2.5 MCR................................................................................................................................................. 137
10.8.2.6 LSR .................................................................................................................................................. 138
10.8.2.7 MSR ................................................................................................................................................. 139
10.8.2.8 SCR .................................................................................................................................................. 140
10.8.2.9 UartEn .............................................................................................................................................. 140
10.8.3 FIFO Interrupt Mode Operation .............................................................................................................. 140
10.9 WATCHDOG TIMER............................................................................................................................................. 142
10.9.1 Watchdog Timer Operation....................................................................................................................... 142
10.9.1.1 The Watchdog Timer Mode .............................................................................................................. 142
10.9.1.2 The Interval Timer Mode.................................................................................................................. 142
10.9.1.3 Timing of setting the overflow flag .................................................................................................. 143
10.9.1.4 Timing of clearing the overflow flag ................................................................................................ 143
10.9.2 Registers................................................................................................................................................... 143
10.9.2.1 WDT Control Register (WDTCTRL)............................................................................................... 143
10.9.2.2 WDT Status Register (WDTSTAT) .................................................................................................. 144
10.9.2.3 WDT Counter (WDTCNT)............................................................................................................... 144
10.9.3 Examples of Register Setting .................................................................................................................... 145
10.9.3.1 Interval Timer Mode......................................................................................................................... 145
10.9.3.2 Watchdog Timer Mode with Internal Reset Disable ......................................................................... 145
10.9.3.3 Watchdog Timer Mode with Manual Reset ...................................................................................... 146
11 DEBUG AND TEST INTERFACE ................................................................................................................... 147
11.1 OVERVIEW......................................................................................................................................................... 147
11.2 SOFTWARE DEVELOPMENT DEBUG AND TEST INTERFACE ................................................................................... 147
11.3 TEST ACCESS PORT AND BOUNDARY-SCAN ........................................................................................................ 147
11.3.1 Reset ......................................................................................................................................................... 148
11.3.2 Pull up Resistors....................................................................................................................................... 148
11.3.3 Instruction Register .................................................................................................................................. 149
11.3.4 Public Instructions ................................................................................................................................... 149
11.3.5 Test Data Registers................................................................................................................................... 151
11.3.6 Boundary Scan Interface Signals ............................................................................................................. 152
11.4 PRODUCTION TEST FEATURES ............................................................................................................................ 160
12 ELECTRICAL CHARACTERISTICS ............................................................................................................ 161
© 2004 MagnaChip Semiconductor Ltd. All Rig6 hts Reserved.
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Version 1.1
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