MAX5104 データシートの表示（PDF） - Maxim Integrated
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MAX5104 Datasheet PDF : 12 Pages
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Low-Power, Dual, Voltage-Output, 12-Bit DAC
with Serial Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V ±10%, VREFA = VREFB = +2.048V, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values
are at TA = +25°C (OS_ connected to AGND for a gain of +2V/V).)
PARAMETER
SYMBOL
CONDITIONS
DIGITAL OUTPUTS (DOUT, UPO)
Output High Voltage
VOH ISOURCE = 2mA
Output Low Voltage
VOL
ISINK = 2mA
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
SR
Output Settling Time
Output Voltage Swing
To 1/2LSB of full-scale, VSTEP = 4V
Rail-to-rail (Note 2)
OSA or OSB Input Resistance
ROS_
Time Required to Exit Shutdown
Digital Feedthrough
Digital Crosstalk
CS = VDD, SCLK = 100kHz, VSCLK = 5Vp-p
POWER SUPPLIES
Positive Supply Voltage
Power-Supply Current
VDD
IDD
(Note 3)
Power-Supply Current
in Shutdown
IDD(SHDN) (Note 3)
Reference Current in Shutdown
TIMING CHARACTERISTICS
SCLK Clock Period
tCP
(Note 4)
SCLK Pulse Width High
tCH
SCLK Pulse Width Low
tCL
CS Fall to SCLK Rise
Setup Time
tCSS
MIN TYP MAX UNITS
VDD - 0.5
V
0.13 0.40
V
0.75
V/µs
15
µs
0 to VDD
V
24
34
kΩ
25
µs
5
nVs
5
nVs
4.5
5.5
V
0.5
0.65
mA
2
10
µA
0
±1
µA
100
ns
40
ns
40
ns
40
ns
SCLK Rise to CS Rise
Hold Time
SDI Setup Time
SDI Hold Time
SCLK Rise to DOUT
Valid Propagation Delay
SCLK Fall to DOUT
Valid Propagation Delay
SCLK Rise to CS Fall Delay
CS Rise to SCLK Rise Hold
CS Pulse Width High
tCSH
tDS
tDH
tDO1
CLOAD = 200pF
tDO2
tCS0
tCS1
tCSW
CLOAD = 200pF
0
ns
40
ns
0
ns
80
ns
80
ns
10
ns
40
ns
100
ns
Note 1: Accuracy is specified from code 6 to code 4095.
Note 2: Accuracy is better than 1LSB for VOUT_ greater than 6mV and less than VDD - 50mV. Guaranteed by PSRR test at the
end points.
Note 3: Digital inputs are set to either VDD or DGND, code = 0000 hex, RL = ∞.
Note 4: SCLK minimum clock period includes the rise and fall times.
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