MAX6877 データシートの表示（PDF） - Maxim Integrated

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MAX6877

Dual-/Triple-Voltage, Power-Supply Trackers/Sequencers/Supervisors

Maxim Integrated 

Dual-/Triple-Voltage, Power-Supply

Trackers/Sequencers/Supervisors

VIN_

R1

R2

IN_

MAX6877

MAX6878

SET_ MAX6879

Figure 9. Setting the Undervoltage (UVLO) Thresholds

voltages below the adjusted thresholds to avoid signal-

ing an error. The state of PG/RST and FAULT outputs

does not change while MARGIN is low. PG/RST,

FAULT, and all monitoring functions are disabled while

MARGIN is low. MARGIN makes it possible to vary the

supplies without a need to adjust the thresholds to pre-

vent tracker/sequencer alerts or faults. Drive MARGIN

high or leave it unconnected for normal operating

mode.

Slew-Rate Control Input (SLEW)

The reference ramp voltage slew rate during any con-

trolled power-up/down phase can be programmed in

the 90V/s to 950V/s range by connecting a capacitor

(CSLEW) from SLEW to ground. Use the following for-

mula to calculate the typical slew rate:

Slew Rate = (9.35 x 10-8)/ CSLEW

where slew rate is in V/s and CSLEW is in farads.

The capacitor at CSLEW also sets the FAULT timeout

period (tFAULT) and FAULT retry timeout period

(tRETRY) (see Table 1).

For example, if CSLEW = 100pF, we have tRETRY =

350ms, tFAULT = 21.91ms, slew rate = 935V/s. For

example, if CSLEW = 1nF, we have tRETRY = 3.5s,

tFAULT = 219ms, slew rate = 93.5V/s.

CSLEW is the capacitor on the SLEW pad, and must be

large enough to make the parasitic capacitance negli-

gible. CSLEW should be in the range of 100pF <

CSLEW < 1nF.

Table 1. CSLEW Timing Formulas

TIME PERIOD

Slew Rate

tRETRY

tFAULT

FORMULAS

(9.35 x 10-8) / CSLEW

3.506 x 109 x CSLEW

2.191 x 108 x CSLEW

Limiting Inrush Current

The capacitor connected at SLEW controls the OUT_S

slew rate, thus controlling the inrush current required to

charge the load capacitor at the outputs (OUT_). Using

the programmed slew rate, limit the inrush current by

using the following formula:

IINRUSH = COUT x SR

where IINRUSH is in amperes, COUT is in farads, and SR

is in V/s.

Delay Time Input (DELAY)

To adjust the desired delay period (tDELAY) before

tracking/sequencing is enabled, connect a capacitor

(CDELAY) between DELAY to ground (see Figures 1 to 8).

The selected delay time is also enforced when EN/UV

rises from low to high when all the input voltages

(IN1/IN2/IN3) are present. Use the following formula to

calculate the delay time:

tDELAY = 200µs + (500kΩ x CDELAY)

where tDELAY is in µs and CDELAY is in farads. Leave

DELAY unconnected for the default 200µs delay.

Timeout Period Input (TIMEOUT)

These devices feature a PG/RST timeout period.

Connect a capacitor (CTIMEOUT) from TIMEOUT to

ground to program the PG/RST timeout period. After all

OUT_ outputs exceed their IN_ referenced thresholds

(VTH_PG), PG/RST remains low for the selected timeout

period, tTIMEOUT (see Figure 3):

tTIMEOUT = 200µs + (500kΩ x CTIMEOUT)

where tTIMEOUT is in µs and CTIMEOUT is in farads.

Leave TIMEOUT unconnected for the default 200µs

timeout delay.

Logic-Enable Input (EN/UV)

Drive logic EN/UV input above VEN_R to initiate voltage

tracking/sequencing during the power-up operation.

Drive logic EN/UV below VEN_F to initiate tracking

power-down operation. Connect EN/UV to an external

resistor-divider network to set the external undervoltage

lockout threshold.

OUT1/OUT2/OUT3

The MAX6877 monitors three and MAX6878/MAX6879

monitor two OUT_ outputs to control the tracking/

sequencing performance. After the internal supply

(ABP) exceeds the minimum voltage (2.7V) require-

ments, EN/UV > VEN_R, and IN1/IN2/IN3 are all greater

than their adjusted SET_ thresholds, OUT1/OUT2/OUT3

begin to track or sequence.

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