MAX6877 データシートの表示（PDF） - Maxim Integrated

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MAX6877

Dual-/Triple-Voltage, Power-Supply Trackers/Sequencers/Supervisors

Maxim Integrated 

Dual-/Triple-Voltage, Power-Supply

Trackers/Sequencers/Supervisors

When a fault is detected, for a period of tRETRY, GATE_

remains off and the 100Ω pulldowns are turned on.

After the tRETRY period, the device waits tDELAY and

retries power-up if all power-up conditions are met (see

Figure 8). These include all VSET_ > 0.5V, EN/UV >

VEN_R, OUT_ voltages < VTH_PL. The autoretry period,

tRETRY, is a function of CSLEW; see Table 1.

When the device is in latch mode and a fault occurs,

FAULT asserts and all outputs are latched off. To

unlatch OUT_ after a fault disappears, cycle EN/UV or

cycle VCC and the inputs (IN_) below the 2.7V UVLO

threshold. After EN/UV goes high, the device waits a

tRETRY period then tries to power-up again. If VCC and

all IN_ are cycled below 2.7V, the device tries to power-

up immediately.

Power-Good Output (PG/RST)

The MAX6877/MAX6878 include a power-good (PG/RST)

output. PG/RST is an open-drain output and requires an

external pullup resistor.

All the OUT_ outputs must exceed their IN_ referenced

thresholds (IN_ x VTH_PG) for the selected reset timeout

period tTIMEOUT (see the TIMEOUT Period Input sec-

tion) before PG/RST asserts high. PG/RST stays low for

the selected reset timeout period (tTIMEOUT) after all

the OUT_ voltages exceed their IN_ referenced thresh-

olds. PG/RST goes low when VSET_ < VTH or VEN/UV <

VEN_R (see Figure 3).

Applications Information

MOSFET Selection

The external pass MOSFET is connected in series with

the sequenced power-supply source. Since the load

current and the MOSFET drain-to-source impedance

(RDS) determine the voltage drop, the on characteris-

tics of the MOSFET affect the load supply accuracy.

The MAX6877/MAX6878/MAX6879 fully enhance the

external MOSFET out of its linear range to ensure the

lowest drain-to-source on-impedance. For highest sup-

ply accuracy/lowest voltage drop, select a MOSFET

with an appropriate drain-to-source on-impedance with

a gate-to-source bias of 4.5V to 6.0V.

Layout and Bypassing

For better noise immunity, bypass each of the IN_

inputs to GND with 0.1µF capacitors installed as close

to the device as possible. Bypass ABP to GND with a

1µF capacitor installed as close to the device as possi-

ble. ABP is an internally generated voltage and must

not be used to supply power to external circuitry.

PART

MAX6877

MAX6878

MAX6879

CHANNEL

3

2

2

TIMEOUT

SELECTABLE

Yes

Yes

No

PG/RST

Yes

Yes

No

Selector Guide

MARGIN

VCC

Yes

Yes

Yes

Yes

No

No

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