MAX6880 データシートの表示（PDF） - Maxim Integrated

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MAX6880

Dual-/Triple-Voltage, Power-Supply Sequencers/Supervisors

Maxim Integrated 

Dual-/Triple-Voltage, Power-Supply

Sequencers/Supervisors

Detailed Description

The MAX6880–MAX6883 multivoltage power

sequencers/supervisors monitor three (MAX6880/

MAX6881) and two (MAX6882/MAX6883) system volt-

ages and provide proper power-up and power-down

control for systems requiring voltage sequencing. These

devices ensure the controlled voltages sequence in the

proper order as system power supplies are enabled.

The MAX6880–MAX6883 generate all required voltages

and timing to control up to three external n-channel

pass FETs for the OUT1/OUT2/OUT3 supply voltages.

The MAX6880–MAX6883 feature adjustable undervolt-

age thresholds for each input supply. When all of the

voltages are above the adjusted thresholds these

devices turn on the external n-channel MOSFETs to

sequence the voltages to the system. The outputs are

turned on one after the other, OUT1 first and OUT3 last.

The MAX6880–MAX6883 feature internal charge pumps

to fully enhance the external FETs for low-voltage drops

at highpass currents. The MAX6880/MAX6882 also fea-

ture a power-good output (PG/RST) with a selectable

timeout period that can be used for system reset.

The MAX6880–MAX6883 monitor up to three voltages.

Devices may be configured to exclude any IN_. To dis-

able sequencing operation of any IN_, connect the IN_

to ground (or leave unconnected) and connect SET_ to

a voltage greater than 0.5V. The channel exclusion fea-

ture adds more flexibility to the device in a variety of

different applications. As an example, the MAX6880

can sequence two voltages using IN1 and IN2 while

IN3 is left disabled.

Powering the MAX6880–MAX6883

These devices derive power from either IN1, IN2, or IN3

voltage inputs (see the Functional Diagram). In order to

ensure proper operation, at least one of the IN_ inputs

must be at least +2.7V.

The highest input voltage on IN1/IN2/IN3 supplies

power to the devices. Internal hysteresis ensures that

the supply input that initially powers these devices con-

tinues to power the MAX6880–MAX6883 when multiple

input voltages are within 100mV (typ) of each other.

Sequencing

The sequencing operation can be initiated after all

input conditions for power-up are met VEN/UV > 1.25V

and all SET_ inputs are above the internal SET_ thresh-

old (0.5V). In sequencing mode, the outputs are turned

on sequentially, OUT1 first and OUT3 last. Before turn-

ing on each channel, a delay period is waited (pro-

grammable by connecting a capacitor from DELAY to

ground. The power-up phase for each channel ends

when its output voltage exceeds a fixed percentage

(VTH_PG) of the corresponding IN_ voltage. When all

channels have exceeded these thresholds, PG/RST

asserts high after tTIMEOUT, indicating a successful

sequence.

If there is a fault condition during the initial power-up

sequence, the process is aborted.

When powering down, all outputs turn off simultaneous-

ly, tracking each other. No reverse power-down

sequencing occurs.

The power-supply sequencing operation should be

completed within the selected fault timeout period

(tFAULT) (see Figure 5). The total sequencing time is

extended when the devices must vary the control slew

rate to allow slow supplies to catch up. If the external

FET is too small (RDS is too high for the selected load

current and IN_ source current), the OUT_ voltage may

never reach the control ramp voltage. For a slew rate of

935V/s, a fault is signaled if all outputs have not stabi-

lized within 22ms. For a slew rate of 93.5V/s, a fault is

signaled if sequencing takes too long (more than

219ms).

The fault time period (tFAULT) is set through the capaci-

tor at SLEW (CSLEW). Use the following formula to esti-

mate the fault timeout period:

tFAULT = 2.191 x 108 x CSLEW

Autoretry Function

The MAX6880/MAX6881/MAX6882 feature autoretry

modes to power-on again after a fault condition has been

detected (see the Typical Operating Characteristics).

When a fault is detected, for a period of tRETRY, GATE_

remains off and the 100Ω pulldowns are turned on.

After the tRETRY period, the device waits tDELAY and

retry sequencing if all power-up conditions are met

(see Figure 5). These include all VSET_ > 0.5V, EN/UV >

VEN_R, and OUT_ voltages < VTH_PL. The autoretry

period tRETRY is a function of CSLEW (see Table 1).

Power-Up and Power-Down

During power-up, OUT_ is forced to follow the internal

reference ramp voltage by an internal loop that controls

the GATE_ of the external MOSFET. This phase must

be completed within the adjustable fault timeout period

(tFAULT); otherwise, the part forces a shutdown on all

GATE_.

Once the power-up is completed, a power-down phase

can be initiated by forcing VEN/UV below VEN_F. The

reference voltage ramp ramps down at the capacitor-

adjusted slew rate. The control-loop comparators moni-

tor each OUT_ voltage with respect to the common

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