MAX6880 データシートの表示（PDF） - Maxim Integrated
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MAX6880 Datasheet PDF : 19 Pages
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Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
reference ramp voltage. During ramp down, if an OUT_
voltage is greater than the reference ramp voltage by
more than VTRK, the control loop dynamically stops the
control ramp voltage from decreasing until the slow
OUT_ voltage catches up. If an OUT_ voltage is greater
or less than the reference ramp voltage by more than
VTRK_F, a fault is signaled and the fast-shutdown mode
is initiated. In fast-shutdown mode, a 100Ω pulldown
resistor is connected from OUT_ to GND to quickly dis-
charge capacitance at OUT_, and GATE_ is pulled low
with a strong IGDS current (see Figure 3).
Figure 4 shows the aborted sequencing mode. When
EN/UV goes low before tTIMEOUT expires, all the out-
puts go low, and the device goes into fast shutdown.
Internal Pulldown
To ensure that the OUT_ voltages are not held high by
a large output capacitance after a fault has occurred,
there is a 100Ω internal pulldown at OUT_. The pull-
down ensures that all OUT_ voltages are below VTH_PL
(referenced to GND) before power-up cycling is initiat-
ed. The internal pulldown also ensures a fast discharge
of the output capacitor during fast shutdown and fault
modes. The pulldowns are not present during normal
operation.
Stability Comment
No external compensation is required for sequencing
or slew-rate control.
Inputs
IN1/IN2/IN3
The highest voltage on IN1, IN2, or IN3 supplies power
to the device. The undervoltage threshold for each IN_
supply is set with an external resistor-divider from each
IN_ to SET_ to ground. To disable sequencing on any
IN_, connect IN_ to ground (or leave unconnected) and
connect SET_ to a voltage greater than 0.5V.
Undervoltage Lockout Threshold Inputs (SET_)
The MAX6880/MAX6881 feature three and the MAX6882/
MAX6883 feature two externally adjustable IN_ under-
voltage lockout thresholds (SET1/SET2/SET3). The 0.5V
SET_ threshold enables monitoring IN_ voltages as low
as 0.5V. The undervoltage threshold for each IN_ sup-
ply is set with an external resistor-divider from each IN_
to SET_ to ground (see Figure 6). All SET_ inputs must
be above the internal SET_ threshold (0.5V) to enable
sequencing functionality. Use the following formula to
set the UVLO threshold:
VIN_ = VTH (R1 + R2) / R2
where VIN_ is the undervoltage lockout threshold and
VTH is the 500mV SET threshold.
Margin Input (MARGIN) (MAX6880/MAX6882)
MARGIN allows system-level testing while power sup-
plies are below the normal ranges as adjusted by the
SET_ inputs. Drive MARGIN low before varying system
voltages below the adjusted thresholds to avoid signal-
ing an error. The state of PG/RST does not change
while MARGIN is low. PG/RST and all monitoring func-
tions are disabled while MARGIN is low. MARGIN
makes it possible to vary the supplies without a need to
adjust the thresholds to prevent sequencer alerts. Drive
MARGIN high or leave it unconnected for normal oper-
ating mode.
Slew-Rate Control Input (SLEW)
The reference ramp voltage slew rate during any con-
trolled power-up/down phase can be programmed in
the 90V/s to 950V/s range by connecting a capacitor
(CSLEW) from SLEW to ground. Use the following for-
mula to calculate the typical slew rate:
Slew Rate = (9.35 x 10-8)/ CSLEW
where slew rate is in V/s and CSLEW is in farads.
The capacitor at CSLEW also sets the retry timeout peri-
od (tRETRY), see Table 1.
For example, if CSLEW = 100pF, we have tRETRY =
350ms, tFAULT = 21.91ms, slew rate = 935V/s. For
example, if CSLEW = 1nF, we have tRETRY = 3.5s, slew
rate = 93.5V/s.
CSLEW is the capacitor on SLEW pad, and must be
large enough so the parasitic PC board capacitance is
negligible. CSLEW should be in the range of 100pF <
CSLEW < 1nF.
VIN_
R1
R2
IN_
MAX6880–
MAX6883
SET_
Figure 6. Setting the Undervoltage (UVLO) Thresholds
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