NJU6682 データシートの表示（PDF） - Japan Radio Corporation
部品番号
コンポーネント説明
メーカー
NJU6682 Datasheet PDF : 58 Pages
| |||
NJU6682
Functional Description
(1)Description for each blocks
1-1) Busy Flag (BF)
As for NJU6682, in case of the inner operation, busy flag (BF) doesn't accept an instruction except of "1". In the
status reed instruction, a busy flag is output by the D7 terminal. If cycle time (tcyc) is secured, to check this flag in
front of the instruction isn't necessary and the throughput of the CPU can be substantially improved.
1-2) X-Address Counter
The X-address counter is the 6 bit presettable counter which gives an address for the row of the display data RAM
as shown in figure 1 and is done in +1 increment by the execution of the display data read / write instruction. But,
when the X-address counter reaches the maximum of the exist address, the count locks by the X-address counter.
With to set X-address once again, as for the count lock of cancellation again this counter is independent with
Y-address register.
By the address inverse instruction(ADC), it is possible for X-address decoder to reverse correspondence relation
between X-address and segment output of display data RAM.
1-3)Z-Address counter
The Y-address counter generates an address to the display RAM direction of the line, it is reset when the inner FR
signal switching timing and count up synchronizes with common cycle of NJU6682.
1-4)Y-Address Register
Y-address register is which gives an address to the display data RAM direction of the line as shown in figure 1.
When replacing Y-address from the CPU and accessing to them, it does by the instruction of the set of Y-address.
1-5)Z-Address Register
Z-address register can be generally used for the scrolling of a screen, in addition to the display with the register
which sets the low address of the data RAM which corresponds to the display line ( being the best line generally ) of
COM0. It sets a display beginning line by setting the display beginning address of 9 bits in this register by the
instruction of the set of Z-address.
1-6)Display data RAM
Display data RAM is the bit map RAM which stores the data for the display which corresponds to the LCD pixel
and is composed of 84,480 bits. Each bit of the display data RAM corresponds to 2:1 in case of gray scale display to
each pixel of LCD and in case of Black and White display, it corresponds to 1:1. The relation between the display
data and the LCD in case of gray scale display is as follows.
The relation between Display data and LCD in Gray Scale Display
The Display RAM data : "00" = Gray Scale Level 0 ( setting by the gray scale level select )
The Display RAM data : "01" = Gray Scale Level 1 (
“
)
The Display RAM data : "10" = Gray Scale Level 2 (
“
)
The Display RAM data : "11" = Gray Scale Level 3 (
“
)
The relation between Display data and LCD in Black and White Display
In Positive Display : "1"=Turn-On Display,"0" =Turn-Off Display
In Negative Display: "1"=Turn-Off Display,"0" =Turn-On Display
When the Display method chooses 16 bit access by the gray scale display, because RAM area of X-address = 16
become 8 bits, lower 8bit (D7-D0) is ignored ( Figure 1-1 ). When the display method chooses 16 bit access by the
Black and White display, as for RAM area of X-address = 8 (Layer0) or 40 (Layer1) becomes 4-bits, lower 12 bit
(D11-D0) is ignored. The bus with in access to the Display Data RAM is 8-bit access an d 16-bit access with the 8-bit
/ 16-bit Bus Select instruction. The access can be chosen.
Share Link: 