NAND512-A2C データシートの表示（PDF） - Numonyx -> Micron
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NAND512-A2C Datasheet PDF : 51 Pages
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NAND512-A2C
4
Bus operations
Bus operations
There are six standard bus operations that control the memory. Each of these is described
in this section, see Table 5: Bus operations, for a summary.
4.1
Command Input
Command Input bus operations are used to give commands to the memory. Command are
accepted when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable
is Low and Read Enable is High. They are latched on the rising edge of the Write Enable
signal.
Only I/O0 to I/O7 are used to input commands.
See Figure 17 and Table 20 for details of the timings requirements.
4.2
Address Input
Address Input bus operations are used to input the memory address. Three bus cycles are
required to input the addresses for the 128Mb and 256Mb devices and four bus cycles are
required to input the addresses for the 512Mb and 1Gb devices (refer to Table 6 and
Table 7, Address Insertion).
The addresses are accepted when Chip Enable is Low, Address Latch Enable is High,
Command Latch Enable is Low and Read Enable is High. They are latched on the rising
edge of the Write Enable signal. Only I/O0 to I/O7 are used to input addresses.
See Figure 18 and Table 20 for details of the timings requirements.
4.3
Data Input
Data Input bus operations are used to input the data to be programmed.
Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command
Latch Enable is Low and Read Enable is High. The data is latched on the rising edge of the
Write Enable signal. The data is input sequentially using the Write Enable signal.
See Figure 19, Table 20, and Table 21 for details of the timings requirements.
4.4
Data Output
Data Output bus operations are used to read: the data in the memory array, the Status
Register, the Electronic Signature and the Serial Number.
Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low,
and Command Latch Enable is Low.
The data is output sequentially using the Read Enable signal.
See Figure 20 and Table 21 for details of the timings requirements.
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