NAND512-A2C データシートの表示（PDF） - Numonyx -> Micron
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NAND512-A2C Datasheet PDF : 51 Pages
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Command set
5
Command set
NAND512-A2C
All bus write operations to the device are interpreted by the Command Interface. The
Commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when
the Command Latch Enable signal is high. Device operations are selected by writing
specific commands to the Command Register. The two-step command sequences for
program and erase operations are imposed to maximize data security.
The Commands are summarized in Table 9.
Table 9. Commands
Command
Bus Write operations(1)(2)
1st CYCLE 2nd CYCLE 3rd CYCLE
Command
accepted during
busy
Read A
Read B(3)
Read C
Read Electronic Signature
Read Status Register
Page Program
Copy Back Program
Block Erase
Reset
00h
-
-
01h
-
-
50h
-
-
90h
-
-
70h
-
-
Yes
80h
10h
-
00h
8Ah
(10h)(4)
60h
D0h
-
FFh
-
-
Yes
1. The bus cycles are only shown for issuing the codes. The cycles required to input the addresses or
input/output data are not shown.
2. Any undefined command sequence will be ignored by the device.
3. The Read B command (code 01h) is not used in x16 devices.
4. The Program Confirm command (code 10h) is no more necessary for NAND512-A2C devices. It is optional
and has been maintained for backward compatibility
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