NAND512-A2C データシートの表示（PDF） - Numonyx -> Micron
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NAND512-A2C Datasheet PDF : 51 Pages
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Bus operations
NAND512-A2C
4.5
Write Protect
Write Protect bus operations are used to protect the memory against program or erase
operations. When the Write Protect signal is Low the device will not accept program or erase
operations and so the contents of the memory array cannot be altered. The Write Protect
signal is not latched by Write Enable to ensure protection even during power-up.
4.6
Standby
When Chip Enable is High the memory enters Standby mode, the device is deselected,
outputs are disabled and power consumption is reduced.
Table 5. Bus operations
Bus Operation E
AL CL R
W WP I/O0 - I/O7 I/O8 - I/O15(1)
Command Input VIL
VIL
VIH
VIH Rising X(2)
Command
X
Address Input
VIL VIH VIL VIH Rising X
Address
X
Data Input
VIL VIL VIL VIH Rising X
Data Input
Data Input
Data Output
VIL
VIL
VIL
Fallin
g
VIH
X
Data Output Data Output
Write Protect
X
X
X
X
X
VIL
X
X
Standby
VIH
X
X
X
X
X
X
X
1. Only for x16 devices.
2. WP must be VIH when issuing a program or erase command.
Table 6. Address Insertion, x8 devices(1)(2)
Bus
Cycle
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1st
A7
A6
A5
A4
A3
A2
A1
A0
2nd
A16
A15
A14
A13
A12
A11
A10
A9
3rd
A24
A23
A22
A21
A20
A19
A18
A17
4th
VIL
VIL
VIL
VIL
VIL
VIL
VIL
A25
1. A8 is set Low or High by the 00h or 01h Command, see Section 6.1: Pointer operations.
2. Any additional address input cycles will be ignored.
Table 7. Address Insertion, x16 devices(1)(2)
Bus
Cycle
I/O8-
I/O15
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1st
X
A7
A6
A5
A4
A3
A2
A1
A0
2nd
X
A16
A15
A14
A13
A12
A11
A10
A9
3rd
X
A24
A23
A22
A21
A20
A19
A18
A17
4th(4)
X
VIL
VIL
VIL
VIL
VIL
VIL
VIL
A25
1. A8 is Don’t Care in x16 devices.
2. Any additional address input cycles will be ignored.
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