SC14480 データシートの表示（PDF） - Unspecified

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SC14480

1.8V Single Chip for DECT

Unspecified 

Table 1: Pin Description

PIN NAME

LED3

LED4

TYPE

A1

A1

Miscellaneous

CLK100

PWM[1-0]

ECZ1

DO-BP

DO-BP

DO

ECZ2

DO

DP[3-2]

DP[1-0]

SF

DO-BP

DO

DO-BP

WTF_IN

ADC0

ADC1

ADC2

NTC

DO-BP

A4S

A4S

A4

FLTM[1-0]

A4

Power and supply

LDO_CTRL

A1

RSTn

A5

VBAT

A1

VDDE

DIO

LDORF_CTRL

A1

Drive

(mA)

2.5/5

2.5/5

Reset

state

(Note 2)

I

I

DESCRIPTION

ANALOG INPUT. Current sink for LED 3. Anode of the LED is

connected to max 3.3V (VBAT). Cathode is connected to this pin.

ANALOG INPUT. Current sink for LED group 2. Anode of the

LED is connected to max 3.3V (VBAT). Cathode is connected to

this pin.

8

I-PU OUTPUT. DIP 100 Hz output set by <SLOTZERO> instruction

8

I-PU OUTPUT. Timer 0 PWM 1 or PWM0 outputs

8

I-PU OUTPUT. Gen2DSP output port set by

DSP_ZCROSS1_OUT_REG[15].

8

I-PU OUTPUT. Gen2DSP output port set by

DSP_ZCROSS2_OUT_REG[15]

8

I-PU OUTPUT. DPx_OUT outputs (<R_LDx> DCF groups signals

500

O-0

“ored” with the MicroWire DCF signal. See RF_MONITOR_REG)

8

I-PU OUTPUT. S-field Sync Found signal indicating the 00 or 11 pre-

amble to unique word transition with 96 ns resolution. Used for

debugging purposes

l 8

I-PU OUTPUT. Gen2DSP enable signal used to monitor DSP load

tia I

INPUT. ADC0 input to ADC with programmable input protection

enabled from reset (ADC0_PR_DIS) (Note 4)

n I-PU

INPUT. ADC1 input to ADC with programmable input protection

enabled from reset (ADC1_PR_DIS) (Note 4)

I

INPUT. ADC2 input to ADC with programmable input protection

e(ADC2_PR_DIS) (Note 4). This ADC input is linear from 0-1.35 V

INPUT. Li-Ion NTC protection input. Used to automatically switch

fidoff the charger circuit if this input goes outside specified voltage

ranges. In this mode ADC2_PR_DIS must be set to have the

full input detection range upto 3.45V. To disable the charge

n auto switch-off feature, either

BAT_CTRL2_REG[NTC_DISABLE] must be set within 200ms

o after power up, or the ADC2/NTC pin must be tied to ground.

C-

INPUT. Analog FLASH test signals. In ROM and FLASH device

connect to VSS or left unconnected.

-

O-1

OUTPUT. Supply control signal connected to the base of an

external PNP transistor used as VDD LDO.

8

I-PU INPUT/OUTPUT. Active low Reset input with Schmitt trigger

(200k pull input, open drain output and pull up resistor to internal VDD.

up)

Input may not exceed 2.0V

-

-

INPUT Main Battery supply voltage <5.5V

8

O-1

1.8V Supply for an external EEPROM OUTPUT. Realized with

P1[5] is output P1_OUTPUT_REG[5] =1 at start-up.

INPUT. Supply control signal connected to base of an optional

NPN transistor in case VBAT > 3.45V. This pin must be left

unconnected if not used and BAT_CTRL_REG[LDORF_ON]

must be set 0 to switch off the LDO.

© 2008-2009 SiTel Semiconductor

10

Version: January 21, 2009 v1.0

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