28F128L18 データシートの表示（PDF） - Numonyx -> Micron

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28F128L18

Numonyx™ StrataFlash Wireless Memory (L18)

Numonyx -> Micron 

Numonyx™ StrataFlash® Wireless Memory (L18)

Table 14: AC Read Specifications, 128-Mbit, 1.7 V to 2.0 V (Sheet 2 of 2)

Num

Symbol

Parameter

R12

R13

R15

R16

R17

tELTV

tEHTZ

tGLTV

tGLTX

tGHTZ

CE# low to WAIT valid

CE# high to WAIT high Z

OE# low to WAIT valid

OE# low to WAIT in low-Z

OE# high to WAIT in high-Z

Latching Specifications

Speed

–85

Min

-

Max

14

-

14

-

14

0

-

-

17

Units

ns

ns

ns

ns

ns

Notes

1

1,3

1

1,3

1,3

R101

R102

R103

R104

R105

R106

R108

R111

tAVVH

tELVH

tVLQV

tVLVH

tVHVL

tVHAX

tAPA

tphvh

Clock Specifications

Address setup to ADV# high

CE# low to ADV# high

ADV# low to output valid

ADV# pulse width low

ADV# pulse width high

Address hold from ADV# high

Page address access

RST# high to ADV# high

7

-

ns

1

10

-

ns

-

85

ns

1,6

7

-

ns

1

7

-

ns

7

-

ns

1,4

-

25

ns

1

30

-

ns

1

R200

R201

R202

R203

fCLK

tCLK

tCH/CL

tFCLK/RCLK

CLK frequency

CLK period

CLK high/low time

CLK fall/rise time

Synchronous Specifications

-

54 MHz

18.5

-

ns

1,3

3.5

-

ns

-

3

ns

R301

tAVCH/L

Address setup to CLK

7

-

ns

R302

R303

tVLCH/L

tELCH/L

ADV# low setup to CLK

CE# low setup to CLK

7

-

ns

1

7

-

ns

R304

tCHQV / tCLQV CLK to output valid

-

14

ns

R305

tCHQX

Output hold from CLK

3

-

ns

1,5

R306

tCHAX

Address hold from CLK

7

-

ns

1,4,5

R307

tCHTV

CLK to WAIT valid

-

14

ns

1,5

R311

tCHVL

CLK Valid to ADV# Setup

0

-

ns

1

R312

tCHTX

WAIT Hold from CLK

3

-

ns

1,5

Notes:

1.

See Figure 8, “AC Input/Output Reference Waveform” on page 26 for timing measurements and

maximum allowable input slew rate.

2.

OE# may be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to tELQV.

3.

Sampled, not 100% tested.

4.

Address hold in synchronous burst mode is tCHAX or tVHAX, whichever timing specification is satisfied first.

5.

Applies only to subsequent synchronous reads.

6.

The specifications in Section 7.3 will only be used by customers (1) who desire a 1.35 to 2.0 VCCQ operating range

OR (2) who desire to transition their host controller from a 1.7 V to 2.0 V VCCQ voltage now to a lower range in the

future.

November 2007

251902-12

Datasheet

29

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