28F128L18 データシートの表示（PDF） - Numonyx -> Micron
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28F128L18 Datasheet PDF : 106 Pages
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Numonyx™ StrataFlash® Wireless Memory (L18)
7.5
AC Read Specifications 256-Mbit (VCCQ = 1.7–2.0 V)
Table 15: AC Read Specifications, 256-Mbit, 1.7 V to 2.0 V (Sheet 1 of 2)
Num
Symbol
Parameter
Speed
Asynchronous Specifications
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R15
R16
R17
tAVAV
tAVQV
tELQV
tGLQV
tPHQV
tELQX
tGLQX
tEHQZ
tGHQZ
tOH
tEHEL
tELTV
tEHTZ
tGLTV
tGLTX
tGHTZ
Read cycle time
Address to output valid
CE# low to output valid
OE# low to output valid
VCC = VCCQ = 1.8 V – 2.0 V
VCC = VCCQ = 1.7 V – 2.0 V
VCC = VCCQ = 1.8 V – 2.0 V
VCC = VCCQ = 1.7 V – 2.0 V
VCC = VCCQ = 1.8 V – 2.0 V
VCC = VCCQ = 1.7 V – 2.0 V
RST# high to output valid
CE# low to output in low-Z
OE# low to output in low-Z
CE# high to output in high-Z
OE# high to output in high-Z
Output hold from first occurring address, CE#, or OE# change
CE# pulse width high
CE# low to WAIT valid
CE# high to WAIT high Z
OE# low to WAIT valid
OE# low to WAIT in low-Z
OE# high to WAIT in high-Z
Latching Specifications
R101
R102
tAVVH
tELVH
R103
tVLQV
R104
R105
R106
R108
R111
tVLVH
tVHVL
tVHAX
tAPA
tphvh
Clock Specifications
Address setup to ADV# high
CE# low to ADV# high
ADV# low to output valid
ADV# pulse width low
ADV# pulse width high
Address hold from ADV# high
Page address access
RST# high to ADV# high
VCC = VCCQ = 1.8 V – 2.0
VCC = VCCQ = 1.7 V – 2.0
R200
R201
R202
R203
fCLK
tCLK
tCH/CL
tFCLK/RCLK
CLK frequency
CLK period
CLK high/low time
CLK fall/rise time
Synchronous Specifications
–85
Min
Max
85
-
88
-
-
85
-
88
-
85
-
88
-
20
-
150
0
-
0
-
-
17
-
17
0
-
14
-
-
14
-
14
-
14
0
-
-
17
7
-
10
-
-
85
-
88
7
-
7
-
7
-
-
25
30
-
-
54
18.5
-
3.5
-
-
3
Units Notes
ns
ns
6
ns
ns
1,2
ns
1
ns
1,3
ns
1,2,3
ns
ns
1,3
ns
ns
1
ns
1
ns
1,3
ns
1
ns
1,3
ns
1,3
ns
1
ns
ns
1,6
ns
1
ns
ns
1,4
ns
1
ns
1
MHz
ns
1,3
ns
ns
Datasheet
30
November 2007
251902-12
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