28F256L30 データシートの表示（PDF） - Numonyx -> Micron

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28F256L30

Numonyx™ StrataFlash® Wireless Memory(L30)

Numonyx -> Micron 

Numonyx™ StrataFlash® Wireless Memory (L30)

Table 14: AC Read Specifications, 256-Mbit (Sheet 2 of 2)

Num

Symbol

Parameter

Speed

R8

R9

R10

tEHQZ

tGHQZ

tOH

CE# high to output in high-Z

OE# high to output in high-Z

Output hold from first occurring address, CE#, or

OE# change

R11

R12

R13

R15

R16

R17

tEHEL

tELTV

tEHTZ

tGLTV

tGLTX

tGHTZ

CE# pulse width high

CE# low to WAIT valid

CE# high to WAIT high Z

OE# low to WAIT valid

OE# low to WAIT in low-Z

OE# high to WAIT in high-Z

Latching Specifications

–85

Min

-

Max

24

-

24

0

-

20

-

-

16

-

17

-

17

0

-

-

20

Units

ns

ns

ns

ns

ns

ns

ns

ns

ns

Notes

1,3

1

1

1,3

1

1,3

1,3

R101

R102

R103

R104

R105

R106

R108

R111

tAVVH

tELVH

tVLQV

tVLVH

tVHVL

tVHAX

tAPA

tphvh

Address setup to ADV# high

10

-

ns

CE# low to ADV# high

10

-

ns

VCC = 1.8 V – 2.0

-

85

ADV# low to output valid

ns

1

VCC = 1.7 V – 2.0

-

88

ADV# pulse width low

10

-

ns

ADV# pulse width high

10

-

ns

Address hold from ADV# high

9

-

ns

1,4

Page address access

-

25

ns

1

RST# high to ADV# high

30

-

ns

1

Clock Specifications

R200

R201

R202

R203

fCLK

tCLK

tCH/CL

tFCLK/RCLK

CLK frequency

CLK period

CLK high/low time

CLK fall/rise time

Synchronous Specifications

-

52

MHz

19.2

-

9

-

ns

1,3

ns

-

3

ns

R301

tAVCH/L

Address setup to CLK

9

-

ns

R302

R303

tVLCH/L

tELCH/L

ADV# low setup to CLK

CE# low setup to CLK

9

-

ns

1

9

-

ns

R304

tCHQV / tCLQV

CLK to output valid

-

17

ns

R305

tCHQX

Output hold from CLK

3

-

ns

1,5

R306

tCHAX

Address hold from CLK

10

-

ns

1,4,5

R307

tCHTV

CLK to WAIT valid

-

17

ns

1,5

R311

tCHVL

CLK Valid to ADV# Setup

0

-

ns

1

R312

tCHTX

WAIT Hold from CLK

3

-

ns

1,5

Notes:

1.

See Figure 8, “AC Input/Output Reference Waveform” on page 25 for timing measurements and max

allowable input slew rate.

2.

OE# may be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to tELQV.

3.

Sampled, not 100% tested.

4.

Address hold in synchronous burst mode is tCHAX or tVHAX, whichever timing specification is satisfied first.

5.

Applies only to subsequent synchronous reads.

Datasheet

28

November 2007

Order Number: 251903-11

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