AD9139(Rev0) データシートの表示（PDF） - Analog Devices

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AD9139
(Rev.:Rev0)

16-Bit, 1600 MSPS, TxDAC+ Digital-to-Analog Converter

Analog Devices 

AD9139

In the continuous reset mode, the FIFO responds to every valid

frame pulse and resets itself. In the one shot reset mode, the

FIFO responds only to the first valid frame pulse after the

FRAME_RESET_MODE bits (Register 0x22[1:0]) are set.

Therefore, even with a continuous frame input, the FIFO resets

one time only; this prevents the FIFO from toggling between

the two states from periodic resets. The one shot frame reset

mode is the default and the recommended mode.

The recommended procedure for a frame initiated FIFO reset is

as follows:

1. Configure the DAC in the desired interpolation mode

(Register 0x28[7]).

2. Ensure that the DACCLK and DCI clocks are running and

stable at the clock inputs.

3. Ensure that the DLL is locked (if using DLL Mode) or the

DCI clock is being sent properly (if using bypass mode).

4. Program Register 0x23 to 0x41.

5. Configure the FRAME_RESET_MODE bits

(Register 0x22[1:0]) to 10.

6. Choose one shot frame mode by writing 0 to

EN_CON_FRAME_RESET (Register 0x22[2]).

7. Toggle the frame input from 0 to 1 and back to 0. The pulse

width must be longer than the minimum requirement.

8. Read back Register 0x06[2] and Register 0x06[1]. If both

bits are 0, continue to Step 9. If any of the two bits are 1,

program Register 0x23 to 0x40.

9. Read back Register 0x24 multiple times to verify that the

actual FIFO level is set to the requested level (Register 0x23)

and the readback values are stable. By design, the readback

should be within ±1 DACCLK around the requested level.

Data Sheet

These procedures apply in synchronization off mode only. For

resetting FIFO in synchronization on mode, refer to the

synchronization procedure in the Multidevice Synchronization

and Fixed Latency section. FIFO reset is one of the steps to

achieve synchronization.

Monitoring the FIFO Status

Monitor the real-time FIFO status from SPI Register 0x24, which

reflects the real-time FIFO depth after a FIFO reset. Without

timing drifts in the system, this readback does not change from

that which resulted from the FIFO reset. When there is a timing

drift or other abnormal clocking situation, the FIFO level

readback can change. However, as long as the FIFO does not

overflow or underflow, there is no error in data trans-mission.

The status bits in Register 0x06, Bits[2:1] indicate if there are

FIFO underflows or overflows. Latch the status of the two bits

to trigger the hardware interrupts, IRQ1 and IRQ2. To enable

latching and interrupts, configure the corresponding bits in

Register 0x03 and Register 0x04.

Rev. 0 | Page 26 of 56

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