AD9923A データシートの表示（PDF） - Analog Devices

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AD9923A

CCD Signal Processor with V-Driver and Precision Timing Generator

Analog Devices 

AD9923A

Increasing H-Clock Width During HBLK

The AD9923A allows the H1 to H4 pulse width to be increased

during the HBLK interval. The H-clock pulse width can in-

crease by reducing the H-clock frequency (see Table 14).

The HBLKWIDTH register (Register 0x35, Bits[6:4]) is a 3-bit

register that allows the H-clock frequency to be reduced by 1/2,

1/4, 1/6, 1/8, 1/10, 1/12, or 1/14. The reduced frequency only

occurs for H1 to H4 pulses that are located within the HBLK area.

be used, such as adding a separate sequence to clamp during the

entire line of OB pixels. This requires configuring a separate

V-sequence for reading the OB lines.

The CLPMASKSTART and CLPMASKEND registers can be used

to disable the CLPOB on a few lines without affecting the setup of

the clamp sequences.

Horizontal Timing Sequence Example

Figure 33 shows an example of a CCD layout. The horizontal

register contains 28 dummy pixels that occur on each line

clocked from the CCD. In the vertical direction, there are 10

optical black (OB) lines at the front of the readout and two at

the back of the readout. The horizontal direction has four OB

pixels in the front and 48 OB pixels in the back.

V

EFFECTIVE IMAGE AREA

2 VERTICAL

OB LINES

10 VERTICAL

OB LINES

Figure 34 shows the basic sequence layout to use during the

effective pixel readout. The 48 OB pixels at the end of each line

are used for CLPOB signals. PBLK is optional and it is often

used to blank the digital outputs during the noneffective CCD

pixels. HBLK is used during the vertical shift interval.

H

4 OB PIXELS

48 OB PIXELS

HORIZONTAL CCD REGISTER

The HBLK, CLPOB, and PBLK parameters are programmed in

the V-sequence registers. More elaborate clamping schemes can

28 DUMMY PIXELS

Figure 33. CCD Configuration Example

Table 14. HBLK Width Register

Register

Length (Bits) Range

HBLKWIDTH 3

1× to 1/14× pixel rate

Description

Controls H1 to H4 width during HBLK as a fraction of pixel rate

0: same frequency as the pixel rate

1: 1/2 pixel frequency, that is, doubles the H1 to H4 pulse width

2: 1/4 pixel frequency

3: 1/6 pixel frequency

4: 1/8 pixel frequency

5: 1/10 pixel frequency

6: 1/12 pixel frequency

7: 1/14 pixel frequency

OPTICAL BLACK

OPTICAL BLACK

HD

CCDIN

SHP

SHD

HL/H1/H3

H2/H4

HBLK

PBLK

CLPOB

VERTICAL SHIFT

DUMMY

EFFECTIVE PIXELS

OPTICAL BLACK

VERT. SHIFT

Figure 34. Horizontal Sequence Example

Rev. A | Page 23 of 84

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