AD9923A データシートの表示（PDF） - Analog Devices

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AD9923A

CCD Signal Processor with V-Driver and Precision Timing Generator

Analog Devices 

AD9923A

VERTICAL TIMING GENERATION

The AD9923A provides a very flexible solution for generating

vertical CCD timing; it can support multiple CCDs and different

system architectures. The 13-phase vertical transfer clocks, XV1 to

XV13, are used to shift lines of pixels into the horizontal output

register of the CCD. The AD9923A allows these outputs to be

individually programmed into various readout configurations,

using a four-step process as shown in Figure 35.

1. Use the vertical pattern group registers to create the individual

pulse patterns for XV1 to XV13.

2. Use the V-pattern groups to build the sequences and add more

information.

3. Construct the readout for an entire field by dividing the field

into regions and assigning a sequence to each region. Each

field can contain up to nine regions to accommodate different

steps, such as high speed line shifts and unique vertical line

transfers, of the readout. The total number of V-patterns,

V-sequences, and fields are programmable and limited by the

number of registers. High speed line shifts and unique vertical

transfers are examples of the different steps required for

readout.

4. Use the MODE register to combine fields in any order for

various readout configurations.

1

CREATE THE VERTICAL PATTERN GROUPS,

UP TO FOUR TOGGLE POSITIONS FOR EACH OUTPUT.

XV1

XV2

XV3

VPAT 0

XV11

XV12

2

BUILD THE V-SEQUENCES BY ADDING START POLARITY,

LINE START POSITION, NUMBER OF REPEATS, ALTERNATION,

GROUP A/B INFORMATION, AND HBLK/CLPOB PULSES.

XV1

XV2

XV3

V-SEQUENCE 0

(VPAT0, 1 REP)

XV11

XV12

XV1

XV2

XV3

VPAT 1

XV11

XV12

XV1

XV2

XV3

V-SEQUENCE 1

(VPAT1, 2 REP)

XV11

XV12

XV1

XV2

XV3

V-SEQUENCE 2

(VPAT1, N REP)

XV11

XV12

USE THE MODE REGISTER TO CONTROL WHICH FIELDS

4 ARE USED, AND IN WHAT ORDER (MAXIMUM OF SEVEN

FIELDS MAY BE COMBINED IN ANY ORDER).

FIELD 0

FIELD 1

FIELD 2

FIELD 3

FIELD 4

3

BUILD EACH FIELD BY DIVIDING IT INTO DIFFERENT

REGIONS AND ASSIGNING A V-SEQUENCE TO EACH

(MAXIMUM OF NINE REGIONS IN EACH FIELD).

FIELD 0

REGION 0: USE V-SEQUENCE 2

REGION 1: USE V-SEQUENCE 0

REGION 2: USE V-SEQUENCE 3

REGION 3: USE V-SEQUENCE 0

FIELD 5

FIELD 1

FIELD 4

FIELD 2

REGION 4: USE V-SEQUENCE 2

FIELD 1

FIELD 2

Figure 35. Summary of Vertical Timing Generation

Rev. A | Page 24 of 84

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