NX26F640C-3T データシートの表示（PDF） - NexFlash -> Winbond Electronics

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NX26F640C-3T

64M-BIT SERIAL FLASH MEMORY WITH 2-PIN NXS2 INTERFACE

NexFlash -> Winbond Electronics 

NX26F640C

ST15 ST14 ST13 ST12 ST11 ST10 ST9 ST8 ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST0

X =RESERVED Busy TR0 TR1 WE X X

X PD DI1 DI0 X X X X

XX

MEMORY ARRAY READY/BUSY

SRAM TRANSFER OR REFRESH

FLASH ARRAY WRITE ENABLE/DISABLE

DATA INTEGRITY STATUS

POWER DETECT

Figure 7. Status Register Bit Locations

Write Enable/Disable, WE

The WE status bit is located at bit ST[12] of the status

register. The bit provides write protect status of global Write

Enable and Write Disable commands. Upon power-up the

WE bit resets to 0.

WE=1 Write Enabled, array can be written to.

WE=0 Write Disabled, array can not be written to.

Power Detect, PD

The Power Detect bit ST[8] works in conjunction with the

Set Power Detection and Reset Power Detection

Commands and is primarily used for removable media

applications. The Set Power Detect Command must be

issued before the PD bit can be used for power detection.

PD=0 Power has been removed

PD=1 Power has not been removed

Data Intergrity Status (DI1, DI0)

The Data Integrity status bits provide an indication of the

data integrity of the last sector that was tranfered to the

SRAM. The bits should be checked after every transfer

sector to SRAM operation.

DII, DI0 = 00 Sector data valid

DII, DI0 = 01 Sector data valid

DII, DI0 = 10 Reserved

DII, DI0 = 11 Sector data error

If DI1 and DI0 = 00 or 01, data is valid and no action is

required. If DI0 and DI1 = 11 a data read error has

occurred. Possible cause for a data error might be exces-

sive system noise, improper power supply levels during

the read or write operation, or excessive erase/write cycles.

Contact NexFlash applications department for further

information regarding handling data error status.

NexFlash Technologies, Inc.

11

PRELIMINARY NXSF020D-0902

09/05/02 ©

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