NX25F641C データシートの表示（PDF） - NexFlash -> Winbond Electronics

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NX25F641C

64M-BIT SERIAL FLASH MEMORY WITH 4-PIN SPI INTERFACE

NexFlash -> Winbond Electronics 

NX25F641C

ST15 ST14 ST13 ST12 ST11 ST10 ST9 ST8 ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST0

X =RESERVED Busy TR0 TR1 WE CNE X

X PD X

XXX XX

XX

MEMORY ARRAY READY/BUSY

SRAM TRANSFER, COMPARE OR REFRESH

FLASH ARRAY WRITE ENABLE/DISABLE

POWER DETECT

SECTOR SRAM COMPARE NOT EQUAL

Figure 6. Status Register Bit Locations

Compare Not Equal, CNE

This bit provides the result of a Compare Sector with

SRAM command. The CNE bit is clear at power-up. At the

complition of a Compare Sector with SRAM command, this

bit is set if the compare failed, clear if the compare

succeded.

Write Enable/Disable, WE

The WE status bit is located at bit ST[12] of the status

register. The bit provides write protect status of global Write

Enable and Write Disable commands. Upon power-up the

WE bit resets to 0.

WE=1 Write Enabled, array can be written to.

WE=0 Write Disabled, array can not be written to.

Power Detect, PD

The Power Detect bit ST[8] works in conjunction with the

Set Power Detection and Reset Power Detection

Commands and is primarily used for removable media

applications. The Set Power Detect Command must be

issued before the PD bit can be used for power detection.

PD=0 Power has been removed

PD=1 Power has not been removed

NexFlash Technologies, Inc.

11

PRELIMINARY NXSF032A-0502

05/06/02 ©

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