CDB53L21 データシートの表示（PDF） - Cirrus Logic

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CDB53L21

Low Power, Stereo Analog to Digital Converter

Cirrus Logic 

4.3.7

CS53L21

Automatic Level Control (ALC)

When enabled, the ALC monitors the analog input signal after the digital attenuator, detects when peak

levels exceed the maximum threshold settings and lowers, first, the PGA gain settings and then increases

the digital attenuation levels at a programmable attack rate and maintains the resulting level below the

maximum threshold.

When input signal levels fall below the minimum threshold, digital attenuation levels are decreased first

and the PGA gain is then increased at a programmable release rate and maintains the resulting level

above the minimum threshold.

Attack and release rates are affected by the ADC soft ramp/zero cross settings and sample rate, Fs. ALC

soft ramp and zero cross dependency may be independently enabled/disabled.

Recommended settings: Best level control may be realized with the fastest attack and slowest release

setting with soft ramp enabled in the control registers. Note: 1.) The maximum realized gain must be set

in the PGAx_VOL register. The ALC will only apply the gain set in the PGAx_VOL. 2.) The ALC maintains

the output signal between the MIN and MAX thresholds. As the input signal level changes, the level-con-

trolled output may not always be the same but will always fall within the thresholds.

Software

Controls:

“ALC Enable & Attack Rate (Address 1Ch)” on page 52, “ALC Release Rate (Address 1Dh)” on

page 52, “ALC Threshold (Address 1Eh)” on page 53, “ALCX & PGAX Control: ALCA, PGAA

(Address 0Ah) & ALCB, PGAB (Address 0Bh)” on page 49.

Input

MIN[2:0]

below full scale

MAX[2:0]

below full scale

ALC

PGA Gain and/or

Attenuator

Output

(after ALC)

MIN[2:0]

below full scale

ADCx_ATT[7:0] and

PGAx_VOL[4:0] volume

controls should NOT be

adjusted manually when

ALCx is enabled.

MAX[2:0]

below full scale

RRATE[5:0]

ARATE[5:0]

Figure 10. ALC

26

DS700PP1

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